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Merge "msm: kgsl: Add GBIF L2 CGC control with A6x CGC"

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qctecmdr 2021-02-01 13:34:01 -08:00 • committed by Gerrit - the friendly Code Review server
commit 08ae823c39
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/msm/adreno_a6xx.c
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@ -49,6 +49,7 @@ static u32 a6xx_pwrup_reglist[] = {
A6XX_SP_NC_MODE_CNTL,
A6XX_PC_DBG_ECO_CNTL,
A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
A6XX_UCHE_GBIF_GX_CONFIG,
};
/* IFPC only static powerup restore list */
@ -372,6 +373,9 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
kgsl_regwrite(device, a6xx_core->hwcg[i].offset,
on ? a6xx_core->hwcg[i].value : 0);
/* GBIF L2 CGC control is not part of the UCHE */
kgsl_regrmw(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x70000, on ? 2 : 0);
/*
* Enable SP clock after programming HWCG registers.
* A612 and A610 GPU is not having the GX power domain.