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ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima

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Explicit MX voting and scaling is required for PCIe on some
chipsets and there are updates to PCIe bus driver to support
this. Although PCIe on shima does not need to explicitly vote for
MX, updates to shima PCIe DT node are required to be compatible
with the new qcom,bw-scale structure. Therefore, add MX entries
to qcom,bw-scale for PCIe on shima.

Change-Id: I4b93b92ee8e401c554e17e769432d3c22998ad98
This commit is contained in:
Tony Truong 2020-10-27 11:25:58 -07:00
commit 0b88f624d5
1 changed files with 12 additions and 4 deletions
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16
qcom/shima-pcie.dtsi
View file

@ -53,10 +53,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;