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ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on lahaina

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Explicit MX voting and scaling is required for PCIe on some
chipsets and there are updates to PCIe bus driver to support
this. Although PCIe on lahaina does not need to explicitly vote
for MX, updates to lahaina PCIe DT nodes are required to be
compatible with the new qcom,bw-scale structure. Therefore, add
MX entries to qcom,bw-scale for both PCIe nodes on lahaina.

Change-Id: If707f61f78e4d99df118ebbfb516d639e5b4f851
This commit is contained in:
Tony Truong 2020-10-26 15:39:06 -07:00
commit 1b25bc8602
1 changed files with 24 additions and 8 deletions
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32
qcom/lahaina-pcie.dtsi
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@ -53,10 +53,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
@ -284,10 +292,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;