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Merge "msm: kgsl: Clean up adreno_spin_idle_debug"

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This commit is contained in:
qctecmdr 2020-08-26 13:02:18 -07:00 • committed by Gerrit - the friendly Code Review server
commit 0cf5ba6fee
7 changed files with 131 additions and 66 deletions
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12
drivers/gpu/msm/a6xx_reg.h
View file

@ -119,7 +119,19 @@
#define A6XX_VSC_ADDR_MODE_CNTL 0xC01
/* LPAC registers */
#define A6XX_CP_LPAC_DRAW_STATE_ADDR 0xB0A
#define A6XX_CP_LPAC_DRAW_STATE_DATA 0xB0B
#define A6XX_CP_LPAC_ROQ_DBG_ADDR 0xB0C
#define A6XX_CP_SQE_AC_UCODE_DBG_ADDR 0xB27
#define A6XX_CP_SQE_AC_UCODE_DBG_DATA 0xB28
#define A6XX_CP_SQE_AC_STAT_ADDR 0xB29
#define A6XX_CP_SQE_AC_STAT_DATA 0xB2A
#define A6XX_CP_LPAC_ROQ_THRESHOLDS_1 0xB32
#define A6XX_CP_LPAC_ROQ_THRESHOLDS_2 0xB33
#define A6XX_CP_LPAC_PROG_FIFO_SIZE 0xB34
#define A6XX_CP_LPAC_ROQ_DBG_DATA 0xB35
#define A6XX_CP_LPAC_FIFO_DBG_DATA 0xB36
#define A6XX_CP_LPAC_FIFO_DBG_ADDR 0xB40
/* RBBM registers */
#define A6XX_RBBM_INT_0_STATUS 0x201

50
drivers/gpu/msm/adreno.c
View file

@ -1801,28 +1801,6 @@ static bool regulators_left_on(struct kgsl_device *device)
return false;
}
int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb)
{
unsigned int *cmds;
int ret;
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
if (cmds == NULL)
return -ENOSPC;
cmds += cp_secure_mode(adreno_dev, cmds, 0);
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)
{
int i;
@ -2822,34 +2800,6 @@ static bool adreno_isidle(struct adreno_device *adreno_dev)
return gpudev->hw_isidle(adreno_dev);
}
/* Print some key registers if a spin-for-idle times out */
void adreno_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr);
adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS, &status);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS3, &status3);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &intstatus);
adreno_readreg(adreno_dev, ADRENO_REG_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
/**
* adreno_spin_idle() - Spin wait for the GPU to idle
* @adreno_dev: Pointer to an adreno device

2
drivers/gpu/msm/adreno.h
View file

@ -660,7 +660,6 @@ enum adreno_regs {
ADRENO_REG_CP_ROQ_DATA,
ADRENO_REG_CP_MEQ_ADDR,
ADRENO_REG_CP_MEQ_DATA,
ADRENO_REG_CP_HW_FAULT,
ADRENO_REG_CP_PROTECT_STATUS,
ADRENO_REG_CP_PREEMPT,
ADRENO_REG_CP_PREEMPT_DEBUG,
@ -925,7 +924,6 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv,
int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb);
void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str);
int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);
int adreno_idle(struct kgsl_device *device);

56
drivers/gpu/msm/adreno_a5xx.c
View file

@ -629,6 +629,34 @@ err:
return ret;
}
static void a5xx_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
kgsl_regread(device, A5XX_CP_RB_RPTR, &rptr);
kgsl_regread(device, A5XX_CP_RB_WPTR, &wptr);
kgsl_regread(device, A5XX_RBBM_STATUS, &status);
kgsl_regread(device, A5XX_RBBM_STATUS3, &status3);
kgsl_regread(device, A5XX_RBBM_INT_0_STATUS, &intstatus);
kgsl_regread(device, A5XX_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
static int _gpmu_send_init_cmds(struct adreno_device *adreno_dev)
{
struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
@ -650,7 +678,7 @@ static int _gpmu_send_init_cmds(struct adreno_device *adreno_dev)
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret != 0)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"gpmu initialization failed to idle\n");
return ret;
@ -1631,7 +1659,7 @@ static int a5xx_post_start(struct adreno_device *adreno_dev)
}
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"hw initialization failed to idle\n");
return ret;
@ -1770,7 +1798,7 @@ static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 20);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"Critical packet submission failed to idle\n");
return ret;
@ -1846,7 +1874,7 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"CP initialization failed to idle\n");
return ret;
@ -1861,6 +1889,7 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_ringbuffer *rb;
uint64_t addr;
unsigned int *cmds;
int ret, i;
/* Clear all the ringbuffers */
@ -1921,11 +1950,21 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
*/
if (!adreno_dev->zap_loaded)
kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0);
else
ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);
else {
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
if (ret)
return ret;
*cmds++ = cp_packet(adreno_dev, CP_SET_SECURE_MODE, 1);
*cmds++ = 0;
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
a5xx_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
}
ret = a5xx_gpmu_init(adreno_dev);
if (ret)
@ -2398,7 +2437,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A5XX_CP_MEQ_DBG_ADDR),
ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A5XX_CP_MEQ_DBG_DATA),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A5XX_CP_PROTECT_REG_0),
ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A5XX_CP_HW_FAULT),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT, A5XX_CP_CONTEXT_SWITCH_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DEBUG, ADRENO_REG_SKIP),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DISABLE, ADRENO_REG_SKIP),

49
drivers/gpu/msm/adreno_a6xx.c
View file

@ -778,6 +778,35 @@ static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev)
return 0;
}
static void a6xx_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
kgsl_regread(device, A6XX_CP_RB_RPTR, &rptr);
kgsl_regread(device, A6XX_CP_RB_WPTR, &wptr);
kgsl_regread(device, A6XX_RBBM_STATUS, &status);
kgsl_regread(device, A6XX_RBBM_STATUS3, &status3);
kgsl_regread(device, A6XX_RBBM_INT_0_STATUS, &intstatus);
kgsl_regread(device, A6XX_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
/*
* a6xx_send_cp_init() - Initialize ringbuffer
* @adreno_dev: Pointer to adreno device
@ -800,7 +829,7 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
adreno_spin_idle_debug(adreno_dev,
a6xx_spin_idle_debug(adreno_dev,
"CP initialization failed to idle\n");
kgsl_sharedmem_writel(device->scratch,
@ -872,7 +901,7 @@ static int a6xx_post_start(struct adreno_device *adreno_dev)
ret = adreno_ringbuffer_submit_spin_nosync(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a6xx_spin_idle_debug(adreno_dev,
"hw preemption initialization failed to idle\n");
return ret;
@ -888,6 +917,7 @@ int a6xx_rb_start(struct adreno_device *adreno_dev)
struct adreno_ringbuffer *rb;
uint64_t addr;
int ret, i;
unsigned int *cmds;
/* Clear all the ringbuffers */
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
@ -946,9 +976,19 @@ int a6xx_rb_start(struct adreno_device *adreno_dev)
if (!adreno_dev->zap_loaded)
kgsl_regwrite(device, A6XX_RBBM_SECVID_TRUST_CNTL, 0);
else {
ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);
if (ret)
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
*cmds++ = cp_packet(adreno_dev, CP_SET_SECURE_MODE, 1);
*cmds++ = 0;
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
a6xx_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
}
return a6xx_post_start(adreno_dev);
@ -2495,7 +2535,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A6XX_CP_RB_WPTR),
ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A6XX_CP_RB_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A6XX_CP_SQE_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A6XX_CP_HW_FAULT),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A6XX_CP_IB1_BASE),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE_HI, A6XX_CP_IB1_BASE_HI),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BUFSZ, A6XX_CP_IB1_REM_SIZE),

2
drivers/gpu/msm/adreno_a6xx_gmu_snapshot.c
View file

@ -55,6 +55,8 @@ static const unsigned int a660_gmu_registers[] = {
0x1F966, 0x1F96B, 0x1F970, 0x1F970, 0x1F972, 0x1F979, 0x1F9CD, 0x1F9D4,
0x1FA02, 0x1FA03, 0x20000, 0x20001, 0x20004, 0x20004, 0x20008, 0x20012,
0x20018, 0x20018,
/* GMU AO LPAC */
0x23B30, 0x23B30,
};
static const unsigned int a630_rscc_snapshot_registers[] = {

26
drivers/gpu/msm/adreno_a6xx_snapshot.c
View file

@ -311,6 +311,10 @@ static const unsigned int a6xx_registers[] = {
static const unsigned int a660_registers[] = {
/* UCHE */
0x0E3C, 0x0E3C,
/* LPAC RBBM */
0x05FC, 0x05FF,
/* LPAC CP */
0x0B00, 0x0B40, 0x0B80, 0x0B83,
};
/*
@ -1839,6 +1843,28 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
A6XX_CP_SQE_UCODE_DBG_ADDR, A6XX_CP_SQE_UCODE_DBG_DATA,
0, 0x8000);
/* CP LPAC indexed registers */
if (adreno_is_a660(adreno_dev)) {
kgsl_snapshot_indexed_registers(device, snapshot,
A6XX_CP_SQE_AC_STAT_ADDR, A6XX_CP_SQE_AC_STAT_DATA,
0, 0x33);
kgsl_snapshot_indexed_registers(device, snapshot,
A6XX_CP_LPAC_DRAW_STATE_ADDR,
A6XX_CP_LPAC_DRAW_STATE_DATA, 0, 0x100);
kgsl_snapshot_indexed_registers(device, snapshot,
A6XX_CP_SQE_AC_UCODE_DBG_ADDR,
A6XX_CP_SQE_AC_UCODE_DBG_DATA, 0, 0x8000);
kgsl_regread(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_2, &roq_size);
roq_size = roq_size >> 14;
kgsl_snapshot_indexed_registers(device, snapshot,
A6XX_CP_LPAC_ROQ_DBG_ADDR,
A6XX_CP_LPAC_ROQ_DBG_DATA, 0, roq_size);
kgsl_snapshot_indexed_registers(device, snapshot,
A6XX_CP_LPAC_FIFO_DBG_ADDR, A6XX_CP_LPAC_FIFO_DBG_DATA,
0, 0x40);
}
/*
* CP ROQ dump units is 4dwords. The number of units is stored
* in CP_ROQ_THRESHOLDS_2[31:16]. Read the value and convert to