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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 07:03:09 -04:00
ARM: dts: msm: fix device tree for validating wb on lahaina
This change adds gdsc voting from mdss_mdp until display rscc is enabled and also removes interface clocks until the dsi interface validation is completed. Change-Id: Ia2841b147fc9b71c2c20d6266b48f7f5ca5d4667
This commit is contained in:
Narendra Muppalla
parent
a439d30fc9
commit
0f113bdb93
3 changed files with 20 additions and 61 deletions
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@ -1 +1 @@
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#include "kona-sde-display.dtsi"
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#include "lahaina-sde-display.dtsi"
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@ -168,38 +168,12 @@
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
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<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
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<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
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<&mdss_dsi0_pll PCLK_SRC_0_CLK>,
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<&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
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<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
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<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
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<&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
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<&mdss_dsi1_pll PCLK_SRC_1_CLK>,
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<&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"src_byte_clk0", "src_pixel_clk0",
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"shadow_byte_clk0", "shadow_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"src_byte_clk1", "src_pixel_clk1",
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"shadow_byte_clk1", "shadow_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi_active &sde_te_active>;
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pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,panel-te-source = <0>;
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vddio-supply = <&pm8150_l14>;
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vdd-supply = <&pm8150a_l11>;
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avdd-supply = <&display_panel_avdd>;
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lab-supply = <&ab_vreg>;
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ibb-supply = <&ibb_vreg>;
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qcom,mdp = <&mdss_mdp>;
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qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
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@ -212,22 +186,11 @@
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
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<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
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<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
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<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
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pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
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qcom,platform-te-gpio = <&tlmm 67 0>;
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qcom,panel-te-source = <1>;
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vddio-supply = <&pm8150_l14>;
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vdd-supply = <&pm8150a_l11>;
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avdd-supply = <&display_panel_avdd>;
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qcom,mdp = <&mdss_mdp>;
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@ -241,19 +204,15 @@
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};
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&sde_dp {
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qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
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qcom,ext-disp = <&ext_disp>;
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,usbplug-cc-gpio = <&tlmm 65 0>;
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pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
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pinctrl-0 = <&sde_dp_usbplug_cc_active>;
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pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
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};
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&mdss_mdp {
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connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
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connectors = <&sde_wb>;
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};
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/* PHY TIMINGS REVISION W */
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@ -31,14 +31,13 @@
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460000000>;
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mmcx-supply = <&VDD_MMCX_LEVEL>;
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vdd-supply = <&disp_cc_mdss_core_gdsc>;
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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@ -265,6 +264,15 @@
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,platform-supply-entry@1 {
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reg = <0>;
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qcom,supply-name = "vdd";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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@ -309,10 +317,7 @@
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sde_dp: qcom,dp_display@ae90000 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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vdda-1p2-supply = <&pm8150_l9>;
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vdda-0p9-supply = <&pm8150_l18>;
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status = "disabled";
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reg = <0xae90000 0x0dc>,
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<0xae90200 0x0c0>,
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@ -341,15 +346,12 @@
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
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<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
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"core_usb_pipe_clk", "link_clk", "link_iface_clk",
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"pixel_clk_rcg", "pixel_parent",
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"pixel1_clk_rcg", "pixel1_parent",
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"pixel_clk_rcg", "pixel1_clk_rcg",
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"strm0_pixel_clk", "strm1_pixel_clk";
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qcom,phy-version = <0x420>;
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@ -419,6 +421,7 @@
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sde_rscc: qcom,sde_rscc@af20000 {
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cell-index = <0>;
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compatible = "qcom,sde-rsc";
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status = "disabled";
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reg = <0xaf20000 0x3c50>,
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<0xaf30000 0x3fd4>;
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reg-names = "drv", "wrapper";
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@ -426,7 +429,7 @@
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qcom,sde-dram-channels = <2>;
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vdd-supply = <&mdss_core_gdsc>;
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vdd-supply = <&disp_cc_mdss_core_gdsc>;
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clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
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<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
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@ -490,7 +493,6 @@
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<25 512 0 6400000>,
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<25 512 0 6400000>;
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rot-vdd-supply = <&mdss_core_gdsc>;
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qcom,supply-names = "rot-vdd";
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clocks =
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@ -546,9 +548,8 @@
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<0xaf08000 0x4>;
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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status = "disabled";
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interrupts = <4 0>;
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vdda-1p2-supply = <&pm8150_l9>;
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refgen-supply = <&refgen>;
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clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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@ -596,9 +597,8 @@
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<0xaf08000 0x4>;
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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status = "disabled";
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interrupts = <5 0>;
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vdda-1p2-supply = <&pm8150_l9>;
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refgen-supply = <&refgen>;
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clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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@ -643,7 +643,7 @@
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reg = <0xae94400 0x7c0>,
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<0xae94200 0x100>;
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reg-names = "dsi_phy", "dyn_refresh_base";
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vdda-0p9-supply = <&pm8150_l5>;
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status = "disabled";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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@ -676,7 +676,7 @@
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reg = <0xae96400 0x7c0>,
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<0xae96200 0x100>;
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reg-names = "dsi_phy", "dyn_refresh_base";
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vdda-0p9-supply = <&pm8150_l5>;
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status = "disabled";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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