mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 14:13:01 -04:00
Merge "ARM: dts: msm: add PMIC devices for SA6150"
This commit is contained in:
qctecmdr
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commit
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6 changed files with 531 additions and 0 deletions
171
qcom/pm6155.dtsi
Normal file
171
qcom/pm6155.dtsi
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@ -0,0 +1,171 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/input/qcom,qpnp-power-on.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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&spmi_bus {
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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qcom,pm6155@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm6155_1_tz: qcom,temp-alarm@2400 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0x2400>;
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interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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qcom,temperature-threshold-set = <1>;
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
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<0x0 0x8 0x1 IRQ_TYPE_NONE>;
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interrupt-names = "kpdpwr", "resin";
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qcom,pon-dbc-delay = <15625>;
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qcom,kpdpwr-sw-debounce;
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qcom,system-reset;
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qcom,store-hard-reset-reason;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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qcom,pull-up = <1>;
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linux,code = <KEY_POWER>;
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};
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qcom,pon_2 {
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qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
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qcom,pull-up;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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pm6155_1_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm6155_1_div_clk1",
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"pm6155_1_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm6155_1_rtc: qcom,pm6155_1_rtc {
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compatible = "qcom,pm8941-rtc";
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#address-cells = <1>;
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#size-cells = <1>;
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qcom,qpnp-rtc-write = <0>;
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qcom,qpnp-rtc-alarm-pwrup = <0>;
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qcom,pm6155_1_rtc_rw@6000 {
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reg = <0x6000 0x100>;
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};
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qcom,pm6155_1_rtc_alarm@6100 {
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reg = <0x6100 0x100>;
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interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
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};
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};
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pm6155_1_gpios: pinctrl@c000 {
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compatible = "qcom,pm8150-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pm6155_1_sdam_2: sdam@b100 {
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compatible = "qcom,spmi-sdam";
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reg = <0xb100 0x100>;
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};
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};
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qcom,pm6155@1 {
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compatible ="qcom,spmi-pmic";
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reg = <1 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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/* below definitions are for the second instance of pm6155 */
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qcom,pm6155@4 {
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compatible = "qcom,spmi-pmic";
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reg = <4 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pm6155_2_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm6155_2_div_clk1",
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"pm6155_2_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm6155_2_gpios: pinctrl@c000 {
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compatible = "qcom,pm8150-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,pm6155@5 {
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compatible ="qcom,spmi-pmic";
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reg = <5 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&thermal_zones {
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pm6155-1-tz {
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polling-delay-passive = <100>;
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polling-delay = <0>;
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thermal-governor = "step_wise";
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thermal-sensors = <&pm6155_1_tz>;
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wake-capable-sensor;
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trips {
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pm6155_trip0: trip0 {
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temperature = <105000>;
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hysteresis = <0>;
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type = "passive";
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};
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pm6155_trip1: trip1 {
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temperature = <125000>;
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hysteresis = <0>;
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type = "critical";
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};
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trip2 {
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temperature = <155000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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@ -1 +1,29 @@
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#include "sa6155-adp-common.dtsi"
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v3-660";
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vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
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vdda-pll-supply = <&pm6155_1_l12>;
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vdda-phy-max-microamp = <30000>;
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vdda-pll-max-microamp = <12000>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm6155_1_l17>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm6155_1_s4>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <600000>;
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qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vddp-ref-clk-min-uV = <1232000>;
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qcom,vddp-ref-clk-max-uV = <1260000>;
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status = "ok"
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};
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@ -1 +1,29 @@
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#include "sa6155-adp-common.dtsi"
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v3-660";
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vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
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vdda-pll-supply = <&pm6155_1_l12>;
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vdda-phy-max-microamp = <30000>;
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vdda-pll-max-microamp = <12000>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm6155_1_l17>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm6155_1_s4>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <600000>;
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qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vddp-ref-clk-min-uV = <1232000>;
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qcom,vddp-ref-clk-max-uV = <1260000>;
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status = "ok"
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};
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@ -40,3 +40,4 @@
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};
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#include "sa6155-regulator.dtsi"
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#include "pm6155.dtsi"
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@ -7,6 +7,12 @@
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qcom,msm-id = <377 0>, <380 0>;
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};
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/* Delete second instance of pm6155 definitions for APQ version */
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&spmi_bus {
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/delete-node/ qcom,pm6155@4;
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/delete-node/ qcom,pm6155@5;
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};
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&apps_rsc {
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/delete-node/ rpmh-regulator-modemlvl;
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/delete-node/ rpmh-regulator-ldoc2;
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297
qcom/sm6150.dtsi
297
qcom/sm6150.dtsi
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@ -7,6 +7,10 @@
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,scc-sm6150.h>
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#include <dt-bindings/clock/qcom,videocc-sm6150.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sm6150.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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@ -21,6 +25,7 @@
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se0_2uart;
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};
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@ -760,6 +765,83 @@
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<WAKE_TCS 1>,
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<ACTIVE_TCS 2>,
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<CONTROL_TCS 0>;
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disp_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
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};
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};
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camnoc_virt: interconnect@0 {
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compatible = "qcom,sm6150-camnoc_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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ipa_virt: interconnect@1 {
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compatible = "qcom,sm6150-ipa_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mc_virt: interconnect@2 {
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compatible = "qcom,sm6150-mc_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos", "disp";
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
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};
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dc_noc: interconnect@9160000 {
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reg = <0x9160000 0x3200>;
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compatible = "qcom,sm6150-dc_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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gem_noc: interconnect@9680000 {
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reg = <0x9680000 0x3E200>;
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compatible = "qcom,sm6150-gem_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos", "disp";
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
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};
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config_noc: interconnect@1500000 {
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reg = <0x1500000 0x5080>;
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compatible = "qcom,sm6150-config_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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system_noc: interconnect@1620000 {
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reg = <0x1620000 0x1F300>;
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compatible = "qcom,sm6150-system_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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aggre1_noc: interconnect@1700000 {
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reg = <0x1700000 0x3F200>;
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compatible = "qcom,sm6150-aggre1_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
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};
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mmss_noc: interconnect@1740000 {
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reg = <0x1740000 0x1C100>;
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compatible = "qcom,sm6150-mmss_noc";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos", "disp";
|
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
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};
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aopcc: qcom,aopcc@0 {
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@ -888,6 +970,221 @@
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#freq-domain-cells = <2>;
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};
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camnoc_virt: interconnect@0 {
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compatible = "qcom,sm6150-camnoc_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
|
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qcom,bcm-voters = <&apps_bcm_voter>;
|
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};
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ipa_virt: interconnect@1 {
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compatible = "qcom,sm6150-ipa_virt";
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#interconnect-cells = <1>;
|
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qcom,bcm-voter-names = "hlos";
|
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qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
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mc_virt: interconnect@2 {
|
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compatible = "qcom,sm6150-mc_virt";
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#interconnect-cells = <1>;
|
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qcom,bcm-voter-names = "hlos", "disp";
|
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
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};
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dc_noc: interconnect@9160000 {
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reg = <0x9160000 0x3200>;
|
||||
compatible = "qcom,sm6150-dc_noc";
|
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#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
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|
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gem_noc: interconnect@9680000 {
|
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reg = <0x9680000 0x3E200>;
|
||||
compatible = "qcom,sm6150-gem_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos", "disp";
|
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
||||
};
|
||||
|
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config_noc: interconnect@1500000 {
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reg = <0x1500000 0x5080>;
|
||||
compatible = "qcom,sm6150-config_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
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system_noc: interconnect@1620000 {
|
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reg = <0x1620000 0x1F300>;
|
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compatible = "qcom,sm6150-system_noc";
|
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#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@1700000 {
|
||||
reg = <0x1700000 0x3F200>;
|
||||
compatible = "qcom,sm6150-aggre1_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1740000 {
|
||||
reg = <0x1740000 0x1C100>;
|
||||
compatible = "qcom,sm6150-mmss_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos", "disp";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
||||
};
|
||||
|
||||
osm_l3: interconnect@18321000 {
|
||||
reg = <0x18321000 0x1400>;
|
||||
compatible = "qcom,sm6150-osm-l3";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
spmi_bus: qcom,spmi@c440000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0xc440000 0x1100>,
|
||||
<0xc600000 0x2000000>,
|
||||
<0xe600000 0x100000>,
|
||||
<0xe700000 0xa0000>,
|
||||
<0xc40a000 0x26000>;
|
||||
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||||
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "periph_irq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
qcom,channel = <0>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
};
|
||||
|
||||
ufsphy_mem: ufsphy_mem@1d87000 {
|
||||
reg = <0x1d87000 0xe00>; /* PHY regs */
|
||||
reg-names = "phy_mem";
|
||||
#phy-cells = <0>;
|
||||
|
||||
lanes-per-direction = <1>;
|
||||
|
||||
clock-names = "ref_clk_src",
|
||||
"ref_clk",
|
||||
"ref_aux_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
||||
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
||||
|
||||
resets = <&ufshc_mem 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufshc_mem: ufshc@1d84000 {
|
||||
compatible = "qcom,ufshc";
|
||||
reg = <0x1d84000 0x3000>,
|
||||
<0x1d90000 0x8000>;
|
||||
reg-names = "ufs_mem", "ufs_ice";
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&ufsphy_mem>;
|
||||
phy-names = "ufsphy";
|
||||
#reset-cells = <1>;
|
||||
|
||||
lanes-per-direction = <1>;
|
||||
limit-phy-submode = <0>;
|
||||
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
||||
spm-level = <5>;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
|
||||
freq-table-hz =
|
||||
<50000000 200000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<37500000 150000000>,
|
||||
<75000000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
||||
interconnect-names = "ufs-ddr", "cpu-ufs";
|
||||
|
||||
qcom,ufs-bus-bw,name = "ufshc_mem";
|
||||
qcom,ufs-bus-bw,num-cases = <12>;
|
||||
qcom,ufs-bus-bw,num-paths = <2>;
|
||||
qcom,ufs-bus-bw,vectors-KBps =
|
||||
/*
|
||||
* During HS G3 UFS runs at nominal voltage corner, vote
|
||||
* higher bandwidth to push other buses in the data path
|
||||
* to run at nominal to achieve max throughput.
|
||||
* 4GBps pushes BIMC to run at nominal.
|
||||
* 200MBps pushes CNOC to run at nominal.
|
||||
* Vote for half of this bandwidth for HS G3 1-lane.
|
||||
* For max bandwidth, vote high enough to push the buses
|
||||
* to run in turbo voltage corner.
|
||||
*/
|
||||
<0 0>, <0 0>, /* No vote */
|
||||
<922 0>, <1000 0>, /* PWM G1 */
|
||||
<1844 0>, <1000 0>, /* PWM G2 */
|
||||
<3688 0>, <1000 0>, /* PWM G3 */
|
||||
<7376 0>, <1000 0>, /* PWM G4 */
|
||||
<127796 0>, <1000 0>, /* HS G1 RA */
|
||||
<255591 0>, <1000 0>, /* HS G2 RA */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RA */
|
||||
<149422 0>, <1000 0>, /* HS G1 RB */
|
||||
<298189 0>, <1000 0>, /* HS G2 RB */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RB */
|
||||
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
||||
|
||||
qcom,bus-vector-names = "MIN",
|
||||
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
||||
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
|
||||
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
|
||||
"MAX";
|
||||
|
||||
reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
non-removable;
|
||||
|
||||
status = "disabled";
|
||||
qos0 {
|
||||
mask = <0xc0>;
|
||||
vote = <67>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0x3f>;
|
||||
vote = <67>;
|
||||
};
|
||||
};
|
||||
|
||||
qmp_aop: qcom,qmp-aop@c300000 {
|
||||
compatible = "qcom,qmp-mbox";
|
||||
reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
|
||||
|
|
|
|||
Loading…
Reference in a new issue