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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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msm: vidc: Align buffer size calculators with num_vpp_pipes
Buffer size calculators are dependent on pipe configuration of the chipset. Ex: Kona has 4 pipes and lagoon has 1 pipe. Hence aligning the buffer size calculators based on chipset specific usage of pipes. Change-Id: I8bb19efc4a80c7e17d9db3cf7d5f1151191b502e Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org> Signed-off-by: Rakshitha Shakamuri <rshakamu@codeaurora.org>
This commit is contained in:
Rakshitha Shakamuri
Gerrit - the friendly Code Review server
parent
833ea5a8b9
commit
1cfa55008e
4 changed files with 111 additions and 93 deletions
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@ -60,7 +60,6 @@
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#define VENUS_DMA_ALIGNMENT BUFFER_ALIGNMENT_SIZE(256)
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#define NUM_OF_VPP_PIPES 4
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#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
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#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64
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#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64
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@ -125,10 +124,9 @@
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#define SIZE_HW_PIC(sizePerBuf) \
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(NUM_HW_PIC_BUF * sizePerBuf)
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#define H264_CABAC_HDR_RATIO_HD_TOT_NUM 1 /* 0.25 */
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#define H264_CABAC_HDR_RATIO_HD_TOT_DEN 4
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#define H264_CABAC_RES_RATIO_HD_TOT_NUM 3 /* 0.75 */
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#define H264_CABAC_RES_RATIO_HD_TOT_DEN 4
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#define H264_CABAC_HDR_RATIO_HD_TOT 1
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#define H264_CABAC_RES_RATIO_HD_TOT 3
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/*
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* some content need more bin buffer, but limit buffer
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* size for high resolution
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@ -182,10 +180,9 @@
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#define SIZE_H265D_QP(width, height) SIZE_H264D_QP(width, height)
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#define H265_CABAC_HDR_RATIO_HD_TOT_NUM 1
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#define H265_CABAC_HDR_RATIO_HD_TOT_DEN 2
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#define H265_CABAC_RES_RATIO_HD_TOT_NUM 1
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#define H265_CABAC_RES_RATIO_HD_TOT_DEN 2
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#define H265_CABAC_HDR_RATIO_HD_TOT 2
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#define H265_CABAC_RES_RATIO_HD_TOT 2
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/*
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* some content need more bin buffer, but limit buffer size
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* for high resolution
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@ -278,31 +275,36 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, bool is_interlaced);
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static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 work_mode, u32 lcu_size);
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u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes);
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static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 work_mode);
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u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);
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static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 work_mode);
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u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);
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static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 work_mode);
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u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);
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static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
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u32 num_vpp_pipes);
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static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
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u32 num_vpp_pipes);
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static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
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u32 num_vpp_pipes);
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static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
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u32 num_vpp_pipes);
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static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);
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u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
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u32 num_vpp_pipes);
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static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 num_ref, bool ten_bit);
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u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);
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static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 num_ref, bool ten_bit);
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u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);
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static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 num_ref, bool ten_bit);
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u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);
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static inline u32 calculate_enc_scratch2_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 num_ref, bool ten_bit);
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@ -369,14 +371,15 @@ static struct msm_vidc_enc_buff_size_calculators vp8e_calculators = {
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int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
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{
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struct msm_vidc_dec_buff_size_calculators *dec_calculators;
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u32 width, height, i, out_min_count;
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u32 width, height, i, out_min_count, num_vpp_pipes;
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struct v4l2_format *f;
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if (!inst) {
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if (!inst || !inst->core || !inst->core->platform_data) {
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d_vpr_e("%s: Instance is null!", __func__);
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return -EINVAL;
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}
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num_vpp_pipes = inst->core->platform_data->num_vpp_pipes;
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f = &inst->fmts[INPUT_PORT].v4l2_fmt;
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switch (f->fmt.pix_mp.pixelformat) {
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case V4L2_PIX_FMT_H264:
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@ -426,7 +429,8 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
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curr_req->buffer_size =
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dec_calculators->calculate_scratch1_size(
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inst, width, height, out_min_count,
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is_secondary_output_mode(inst));
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is_secondary_output_mode(inst),
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num_vpp_pipes);
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valid_buffer_type = true;
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} else if (curr_req->buffer_type ==
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HAL_BUFFER_INTERNAL_PERSIST_1) {
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@ -486,17 +490,18 @@ int msm_vidc_get_num_ref_frames(struct msm_vidc_inst *inst)
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int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
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{
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struct msm_vidc_enc_buff_size_calculators *enc_calculators;
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u32 width, height, i, num_ref;
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u32 width, height, i, num_ref, num_vpp_pipes;
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bool is_tenbit = false;
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int num_bframes;
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struct v4l2_ctrl *bframe;
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struct v4l2_format *f;
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if (!inst) {
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if (!inst || !inst->core || !inst->core->platform_data) {
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d_vpr_e("%s: Instance is null!", __func__);
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return -EINVAL;
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}
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num_vpp_pipes = inst->core->platform_data->num_vpp_pipes;
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f = &inst->fmts[OUTPUT_PORT].v4l2_fmt;
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switch (f->fmt.pix_mp.pixelformat) {
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case V4L2_PIX_FMT_H264:
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@ -537,14 +542,15 @@ int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
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curr_req->buffer_size =
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enc_calculators->calculate_scratch_size(
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inst, width, height,
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inst->clk_data.work_mode);
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inst->clk_data.work_mode,
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num_vpp_pipes);
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valid_buffer_type = true;
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} else if (curr_req->buffer_type ==
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HAL_BUFFER_INTERNAL_SCRATCH_1) {
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curr_req->buffer_size =
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enc_calculators->calculate_scratch1_size(
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inst, width, height, num_ref,
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is_tenbit);
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is_tenbit, num_vpp_pipes);
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valid_buffer_type = true;
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} else if (curr_req->buffer_type ==
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HAL_BUFFER_INTERNAL_SCRATCH_2) {
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@ -987,7 +993,7 @@ u32 msm_vidc_calculate_enc_output_extra_size(struct msm_vidc_inst *inst)
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return ALIGN(size, SZ_4K);
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}
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static inline u32 size_vpss_lb(u32 width, u32 height)
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static inline u32 size_vpss_lb(u32 width, u32 height, u32 num_vpp_pipes)
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{
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u32 vpss_4tap_top_buffer_size, vpss_div2_top_buffer_size;
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u32 vpss_4tap_left_buffer_size, vpss_div2_left_buffer_size;
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@ -1009,7 +1015,7 @@ static inline u32 size_vpss_lb(u32 width, u32 height)
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opb_lb_wr_llb_uv_buffer_size = opb_lb_wr_llb_y_buffer_size =
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ALIGN((ALIGN(height, 16) / 2) *
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64, BUFFER_ALIGNMENT_SIZE(32));
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size = NUM_OF_VPP_PIPES * 2 * (vpss_4tap_top_buffer_size +
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size = num_vpp_pipes * 2 * (vpss_4tap_top_buffer_size +
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vpss_div2_top_buffer_size) +
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2 * (vpss_4tap_left_buffer_size +
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vpss_div2_left_buffer_size) +
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@ -1073,7 +1079,8 @@ static inline u32 size_h264d_vpp_cmd_buf(u32 height)
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return size;
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}
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static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height)
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static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height,
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u32 num_vpp_pipes)
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{
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u32 size;
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u32 size_bse, size_vpp;
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@ -1088,11 +1095,11 @@ static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height)
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ALIGN(SIZE_H264D_LB_FE_TOP_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H264D_LB_FE_LEFT_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
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ALIGN(SIZE_H264D_LB_SE_TOP_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H264D_LB_SE_LEFT_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
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ALIGN(SIZE_H264D_LB_PE_TOP_DATA(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H264D_LB_VSP_TOP(width, height),
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@ -1115,10 +1122,8 @@ static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height)
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((BIN_BUFFER_THRESHOLD * 3) >> 1) :
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((product * 3) >> 1);
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size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT_NUM /
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H264_CABAC_HDR_RATIO_HD_TOT_DEN;
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size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT_NUM /
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H264_CABAC_RES_RATIO_HD_TOT_DEN;
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size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT;
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size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT;
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size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);
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size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);
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size = size_bin_hdr + size_bin_res;
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@ -1132,12 +1137,10 @@ static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst,
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u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));
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u32 size = 0;
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if (!is_interlaced) {
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if (!is_interlaced)
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size = size_h264d_hw_bin_buffer(aligned_width, aligned_height);
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size = size * NUM_OF_VPP_PIPES;
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} else {
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else
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size = 0;
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}
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return size;
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}
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@ -1185,7 +1188,8 @@ static inline u32 hfi_iris2_h265d_comv_size(u32 width, u32 height,
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return size;
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}
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static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height)
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static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height,
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u32 num_vpp_pipes)
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{
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u32 size_bse, size_vpp;
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u32 size = 0;
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@ -1205,9 +1209,9 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height)
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ALIGN(SIZE_H265D_LB_FE_TOP_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H265D_LB_FE_LEFT_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
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ALIGN(SIZE_H265D_LB_SE_LEFT_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
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ALIGN(SIZE_H265D_LB_SE_TOP_CTRL(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H265D_LB_PE_TOP_DATA(width, height),
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@ -1215,7 +1219,7 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height)
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ALIGN(SIZE_H265D_LB_VSP_TOP(width, height),
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VENUS_DMA_ALIGNMENT) +
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ALIGN(SIZE_H265D_LB_VSP_LEFT(width, height),
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VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
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ALIGN(SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height),
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VENUS_DMA_ALIGNMENT) * 4 +
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ALIGN(SIZE_H265D_QP(width, height), VENUS_DMA_ALIGNMENT);
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@ -1233,10 +1237,8 @@ static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height)
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size_yuv = (product <= BIN_BUFFER_THRESHOLD) ?
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((BIN_BUFFER_THRESHOLD * 3) >> 1) :
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((product * 3) >> 1);
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size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT_NUM /
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H265_CABAC_HDR_RATIO_HD_TOT_DEN;
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size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT_NUM /
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H265_CABAC_RES_RATIO_HD_TOT_DEN;
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size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT;
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size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT;
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size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);
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size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);
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size = size_bin_hdr + size_bin_res;
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@ -1251,12 +1253,10 @@ static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst,
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u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));
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u32 size = 0;
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if (!is_interlaced) {
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if (!is_interlaced)
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size = size_h265d_hw_bin_buffer(aligned_width, aligned_height);
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size = size * NUM_OF_VPP_PIPES;
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} else {
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else
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size = 0;
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}
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return size;
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}
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@ -1299,7 +1299,7 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst,
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}
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static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
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u32 width, u32 height, u32 work_mode, u32 lcu_size)
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u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes)
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{
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u32 aligned_width, aligned_height, bitstream_size;
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u32 total_bitbin_buffers = 0, size_singlePipe, bitbin_size = 0;
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@ -1319,7 +1319,10 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
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bitstream_size = aligned_width * aligned_height * 3;
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bitbin_size = ALIGN(bitstream_size, VENUS_DMA_ALIGNMENT);
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}
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size_singlePipe = bitbin_size / 2;
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if (num_vpp_pipes > 2)
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size_singlePipe = bitbin_size / 2;
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else
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size_singlePipe = bitbin_size;
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if (inst->rc_type == RATE_CONTROL_LOSSLESS)
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size_singlePipe <<= 1;
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size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);
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@ -1328,7 +1331,7 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
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padded_bin_size = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);
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size_singlePipe = sao_bin_buffer_size + padded_bin_size;
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size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);
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bitbin_size = size_singlePipe * NUM_OF_VPP_PIPES;
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bitbin_size = size_singlePipe * num_vpp_pipes;
|
||||
size = ALIGN(bitbin_size, VENUS_DMA_ALIGNMENT) * total_bitbin_buffers
|
||||
+ 512;
|
||||
|
||||
|
|
@ -1336,50 +1339,56 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
|
|||
}
|
||||
|
||||
static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 work_mode)
|
||||
u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)
|
||||
{
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 16);
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 16,
|
||||
num_vpp_pipes);
|
||||
}
|
||||
|
||||
static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 work_mode)
|
||||
u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)
|
||||
{
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 32);
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 32,
|
||||
num_vpp_pipes);
|
||||
}
|
||||
|
||||
static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 work_mode)
|
||||
u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)
|
||||
{
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 16);
|
||||
return calculate_enc_scratch_size(inst, width, height, work_mode, 16,
|
||||
num_vpp_pipes);
|
||||
}
|
||||
|
||||
static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes)
|
||||
{
|
||||
u32 co_mv_size = 0, nonco_mv_size = 0;
|
||||
u32 vpss_lb_size = 0;
|
||||
u32 size = 0;
|
||||
|
||||
co_mv_size = hfi_iris2_h264d_comv_size(width, height, min_buf_count);
|
||||
nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height);
|
||||
nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height,
|
||||
num_vpp_pipes);
|
||||
if (split_mode_enabled)
|
||||
vpss_lb_size = size_vpss_lb(width, height);
|
||||
|
||||
vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);
|
||||
size = co_mv_size + nonco_mv_size + vpss_lb_size;
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes)
|
||||
{
|
||||
u32 co_mv_size = 0, nonco_mv_size = 0;
|
||||
u32 vpss_lb_size = 0;
|
||||
u32 size = 0;
|
||||
|
||||
co_mv_size = hfi_iris2_h265d_comv_size(width, height, min_buf_count);
|
||||
nonco_mv_size = hfi_iris2_h265d_non_comv_size(width, height);
|
||||
nonco_mv_size =
|
||||
hfi_iris2_h265d_non_comv_size(width, height, num_vpp_pipes);
|
||||
if (split_mode_enabled)
|
||||
vpss_lb_size = size_vpss_lb(width, height);
|
||||
vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);
|
||||
|
||||
size = co_mv_size + nonco_mv_size + vpss_lb_size +
|
||||
HDR10_HIST_EXTRADATA_SIZE;
|
||||
|
|
@ -1393,16 +1402,17 @@ static inline u32 hfi_iris2_vp8d_comv_size(u32 width, u32 height,
|
|||
}
|
||||
|
||||
static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes)
|
||||
{
|
||||
u32 vpss_lb_size = 0;
|
||||
u32 size = 0;
|
||||
|
||||
size = hfi_iris2_vp8d_comv_size(width, height, 0);
|
||||
size += ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height),
|
||||
VENUS_DMA_ALIGNMENT) +
|
||||
ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
|
||||
|
|
@ -1416,22 +1426,23 @@ static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst,
|
|||
ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),
|
||||
VENUS_DMA_ALIGNMENT);
|
||||
if (split_mode_enabled)
|
||||
vpss_lb_size = size_vpss_lb(width, height);
|
||||
vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);
|
||||
|
||||
size += vpss_lb_size;
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes)
|
||||
{
|
||||
u32 vpss_lb_size = 0;
|
||||
u32 size = 0;
|
||||
|
||||
size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VP9D_LB_VSP_TOP(width, height),
|
||||
VENUS_DMA_ALIGNMENT) +
|
||||
ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
|
||||
|
|
@ -1445,22 +1456,23 @@ static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst,
|
|||
ALIGN(SIZE_VP9D_LB_FE_TOP_DATA(width, height),
|
||||
VENUS_DMA_ALIGNMENT);
|
||||
if (split_mode_enabled)
|
||||
vpss_lb_size = size_vpss_lb(width, height);
|
||||
vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);
|
||||
|
||||
size += vpss_lb_size + HDR10_HIST_EXTRADATA_SIZE;
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)
|
||||
u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes)
|
||||
{
|
||||
u32 vpss_lb_size = 0;
|
||||
u32 size = 0;
|
||||
|
||||
size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),
|
||||
VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +
|
||||
VENUS_DMA_ALIGNMENT) * num_vpp_pipes +
|
||||
ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height),
|
||||
VENUS_DMA_ALIGNMENT) +
|
||||
ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
|
||||
|
|
@ -1474,7 +1486,7 @@ static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst,
|
|||
ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),
|
||||
VENUS_DMA_ALIGNMENT);
|
||||
if (split_mode_enabled)
|
||||
vpss_lb_size = size_vpss_lb(width, height);
|
||||
vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);
|
||||
|
||||
size += vpss_lb_size;
|
||||
return size;
|
||||
|
|
@ -1630,27 +1642,27 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst,
|
|||
}
|
||||
|
||||
static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit)
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)
|
||||
{
|
||||
return calculate_enc_scratch1_size(inst, width, height, 16,
|
||||
num_ref, ten_bit, NUM_OF_VPP_PIPES, false);
|
||||
num_ref, ten_bit, num_vpp_pipes, false);
|
||||
}
|
||||
|
||||
static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit)
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)
|
||||
{
|
||||
return calculate_enc_scratch1_size(inst, width, height, 32,
|
||||
num_ref, ten_bit, NUM_OF_VPP_PIPES, true);
|
||||
num_ref, ten_bit, num_vpp_pipes, true);
|
||||
}
|
||||
|
||||
static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit)
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)
|
||||
{
|
||||
(void)num_vpp_pipes;
|
||||
return calculate_enc_scratch1_size(inst, width, height, 16,
|
||||
num_ref, ten_bit, 1, false);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 hfi_ubwc_calc_metadata_plane_stride(u32 width,
|
||||
u32 metadata_stride_multi, u32 tile_width_pels)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __H_MSM_VIDC_BUFFER_MEM_DEFS_H__
|
||||
|
|
@ -14,15 +14,17 @@ struct msm_vidc_dec_buff_size_calculators {
|
|||
u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width,
|
||||
u32 height, bool is_interlaced);
|
||||
u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst, u32 width,
|
||||
u32 height, u32 min_buf_count, bool split_mode_enabled);
|
||||
u32 height, u32 min_buf_count, bool split_mode_enabled,
|
||||
u32 num_vpp_pipes);
|
||||
u32 (*calculate_persist1_size)(void);
|
||||
};
|
||||
|
||||
struct msm_vidc_enc_buff_size_calculators {
|
||||
u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width,
|
||||
u32 height, u32 work_mode);
|
||||
u32 height, u32 work_mode, u32 num_vpp_pipes);
|
||||
u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit);
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit,
|
||||
u32 num_vpp_pipes);
|
||||
u32 (*calculate_scratch2_size)(struct msm_vidc_inst *inst,
|
||||
u32 width, u32 height, u32 num_ref, bool ten_bit);
|
||||
u32 (*calculate_persist_size)(void);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _MSM_VIDC_INTERNAL_H_
|
||||
|
|
@ -294,6 +294,7 @@ struct msm_vidc_platform_data {
|
|||
unsigned int efuse_data_length;
|
||||
unsigned int sku_version;
|
||||
uint32_t vpu_ver;
|
||||
uint32_t num_vpp_pipes;
|
||||
struct msm_vidc_ubwc_config_data *ubwc_config;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
|
@ -552,6 +552,7 @@ static struct msm_vidc_platform_data default_data = {
|
|||
.efuse_data_length = 0,
|
||||
.sku_version = 0,
|
||||
.vpu_ver = VPU_VERSION_IRIS2,
|
||||
.num_vpp_pipes = 0x4,
|
||||
.ubwc_config = 0x0,
|
||||
};
|
||||
|
||||
|
|
@ -567,6 +568,7 @@ static struct msm_vidc_platform_data lahaina_data = {
|
|||
.efuse_data_length = 0,
|
||||
.sku_version = 0,
|
||||
.vpu_ver = VPU_VERSION_IRIS2,
|
||||
.num_vpp_pipes = 0x4,
|
||||
.ubwc_config = lahaina_ubwc_data,
|
||||
.codecs = default_codecs,
|
||||
.codecs_count = ARRAY_SIZE(default_codecs),
|
||||
|
|
@ -586,6 +588,7 @@ static struct msm_vidc_platform_data bengal_data = {
|
|||
.efuse_data_length = 0,
|
||||
.sku_version = 0,
|
||||
.vpu_ver = VPU_VERSION_AR50_LITE,
|
||||
.num_vpp_pipes = 0x1,
|
||||
.ubwc_config = 0x0,
|
||||
.codecs = bengal_codecs,
|
||||
.codecs_count = ARRAY_SIZE(bengal_codecs),
|
||||
|
|
|
|||
Loading…
Reference in a new issue