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Merge 97e93b7430 on remote branch

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Change-Id: I3371afe51a55c06b52494d49b1b04a8801577c3c
This commit is contained in:
Linux Build Service Account 2021-02-22 00:36:10 -08:00
commit 1e5011b60a
8 changed files with 177 additions and 9 deletions
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41
display/lahaina-sde-display.dtsi
View file

@ -1,4 +1,5 @@
#include "lahaina-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
&tlmm {
display_panel_avdd_default: display_panel_avdd_default {
@ -59,7 +60,22 @@
<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>;
<&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
@ -69,7 +85,8 @@
"cphy_byte_clk1", "cphy_pixel_clk1",
"src_byte_clk1", "src_pixel_clk1",
"shadow_byte_clk1", "shadow_pixel_clk1",
"shadow_cphybyte_clk1", "shadow_cphypixel_clk1";
"shadow_cphybyte_clk1", "shadow_cphypixel_clk1",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@ -93,11 +110,27 @@
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
"cphy_byte_clk1", "cphy_pixel_clk1",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;

26
display/trustedvm-yupik-sde-display.dtsi Normal file
View file

@ -0,0 +1,26 @@
#include "yupik-sde-display-common.dtsi"
&sde_dsi {
clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>,
<&clock_cpucc PCLK_MUX_0_CLK>,
<&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>,
<&clock_cpucc CPHY_PCLK_SRC_0_CLK>,
<&clock_cpucc BYTECLK_SRC_0_CLK>,
<&clock_cpucc PCLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_PCLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_CPHY_PCLK_SRC_0_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
qcom,panel-te-source = <0>;
qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>;
};
&mdss_mdp {
connectors = <&sde_dsi>;
};

55
display/trustedvm-yupik-sde.dtsi Normal file
View file

@ -0,0 +1,55 @@
#include "yupik-sde-common.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
};
&mdss_mdp {
reg = <0x0ae00000 0x84000>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x800>,
<0x0ae8f000 0x02c>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"sid_phys";
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,sde-hw-version = <0x70020000>;
clocks =
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>,
<&clock_cpucc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
qcom,sde-trusted-vm-env;
qcom,vram-size = <0x200000>;
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};

4
display/yupik-sde-common.dtsi
View file

@ -193,10 +193,6 @@
qcom,sde-secure-sid-mask = <0x901 0xD01>;
/* SPMI address related to display */
qcom,pmic-arb = <&spmi_bus>;
qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>;
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 74000>,
<0 148000>,

32
display/yupik-sde-display-common.dtsi
View file

@ -1,4 +1,5 @@
#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi"
#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi"
#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi"
#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi"
@ -125,10 +126,17 @@
};
&dsi_nt36672e_fhd_plus_144_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,dsi-supported-dfps-list = <144 120 60 48>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,mdss-dsi-qsync-min-refresh-rate = <48>;
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list =
<953341056 946720632 950030848>;
qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
@ -139,6 +147,28 @@
};
};
&dsi_nt36672e_fhd_plus_120_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,dsi-supported-dfps-list = <120 60 48>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,mdss-dsi-qsync-min-refresh-rate = <48>;
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-list =
<901327680 893816616 897572152>;
qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08
08 08 02 04 00 1b 18];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt36672e_fhd_plus_60_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
qcom,mdss-dsi-display-timings {

18
display/yupik-sde-display-idp.dtsi
View file

@ -8,6 +8,14 @@
qcom,platform-reset-gpio = <&tlmm 44 0>;
};
&dsi_nt36672e_fhd_plus_120_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 44 0>;
};
&dsi_nt36672e_fhd_plus_60_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
@ -26,6 +34,16 @@
qcom,platform-reset-gpio = <&tlmm 44 0>;
};
&dsi_r66451_amoled_120hz_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 44 0>;
};
&dsi_r66451_amoled_144hz_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

9
display/yupik-sde-display.dtsi
View file

@ -59,6 +59,15 @@
qcom,mdss-dsi-panel-status-read-length = <1>;
};
&dsi_nt36672e_fhd_plus_120_video {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
};
&dsi_r66451_amoled_60hz_cmd_cphy {
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";

1
display/yupik-sde.dtsi
View file

@ -207,5 +207,6 @@
vdda-0p9-supply = <&L10C>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
memory-region = <&dfps_data_memory>;
};