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Merge "ARM: dts: msm: Add support for ddr scaling on sdxlemur"
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70
bindings/arm/pmu.txt
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70
bindings/arm/pmu.txt
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* ARM Performance Monitor Units
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm,cortex-a73-pmu"
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"arm,cortex-a72-pmu"
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"arm,cortex-a57-pmu"
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"arm,cortex-a53-pmu"
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"arm,cortex-a35-pmu"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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"arm,cortex-a12-pmu"
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"arm,cortex-a9-pmu"
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"arm,cortex-a8-pmu"
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"arm,cortex-a7-pmu"
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"arm,cortex-a5-pmu"
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"arm,arm11mpcore-pmu"
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"arm,arm1176-pmu"
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"arm,arm1136-pmu"
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"brcm,vulcan-pmu"
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"cavium,thunder-pmu"
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"qcom,scorpion-pmu"
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"qcom,scorpion-mp-pmu"
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"qcom,krait-pmu"
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- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
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interrupt (PPI) then 1 interrupt should be specified.
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Optional properties:
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- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
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nodes corresponding directly to the affinity of
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the SPIs listed in the interrupts property.
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When using a PPI, specifies a list of phandles to CPU
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nodes corresponding to the set of CPUs which have
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a PMU of this type signalling the PPI listed in the
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interrupts property, unless this is already specified
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by the PPI interrupt specifier itself (in which case
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the interrupt-affinity property shouldn't be present).
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This property should be present when there is more than
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a single SPI.
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- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
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events.
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- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
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(SDER) is accessible. This will cause the driver to do
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any setup required that is only possible in ARMv7 secure
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state. If not present the ARMv7 SDER will not be touched,
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which means the PMU may fail to operate unless external
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code (bootloader or security monitor) has performed the
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appropriate initialisation. Note that this property is
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not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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in Non-secure state.
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Example:
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <100 101>;
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};
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@ -11,6 +11,9 @@
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/spmi/spmi.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -277,6 +280,11 @@
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};
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};
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cpu_pmu: cpu-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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qcom,msm-imem@1468f000 {
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compatible = "qcom,msm-imem";
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reg = <0x1468f000 0x1000>; /* Address and size of IMEM */
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@ -474,6 +482,50 @@
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status = "disabled";
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};
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ddr_bw_opp_table: ddr-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 100, 4); /* 381 MB/s */
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BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
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BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
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BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
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BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
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BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
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BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
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BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */
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BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */
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BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */
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BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */
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BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */
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};
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cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
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compatible = "qcom,devfreq-icc";
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governor = "compute";
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interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu0_cpu_ddr_tbl: qcom,cpu0-cpu-ddr-tbl {
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qcom,core-dev-table =
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< 345600 MHZ_TO_MBPS( 300, 4) >,
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< 576000 MHZ_TO_MBPS( 768, 4) >,
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< 1440000 MHZ_TO_MBPS(1555, 4) >,
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< 1497600 MHZ_TO_MBPS(2092, 4) >;
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};
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memlat_cpugrp: qcom,memlat-cpugrp {
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compatible = "qcom,arm-memlat-cpugrp";
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qcom,cpulist = <&CPU0>;
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cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
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compatible = "qcom,arm-compute-mon";
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qcom,cpulist = <&CPU0>;
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qcom,target-dev = <&cpu0_cpu_ddr_lat>;
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qcom,core-dev-table = <&cpu0_cpu_ddr_tbl>;
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};
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};
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sdhc_1: sdhci@8804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x08804000 0x1000>;
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