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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add UFS support for SA8155
Add UFS host controller and UFS PHY (attached to embedded UFS card) for SM8150 platform and SA8155. Change-Id: I2f58f3bd2457fed0baaffa5233bbd2c92ec22c12
This commit is contained in:
Veera Vegivada
parent
6236ec35c7
commit
24f8b6eb0b
3 changed files with 169 additions and 0 deletions
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@ -1,2 +1,27 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-pll-supply = <&pm8150_2_l8>;
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vdda-phy-max-microamp = <87100>;
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vdda-pll-max-microamp = <18300>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8150_1_l10>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm8150_1_s4>;
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vcc-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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status = "ok"
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};
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@ -68,3 +68,7 @@
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&gpu_gx_gdsc {
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parent-supply = <&VDD_GFX_LEVEL>;
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};
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&ufsphy_mem {
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vdda-phy-supply = <&pm8150_2_l18>;
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};
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140
qcom/sm8150.dtsi
140
qcom/sm8150.dtsi
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@ -6,6 +6,7 @@
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#include <dt-bindings/clock/qcom,npucc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8150.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@ -24,6 +25,7 @@
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &uart2;
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};
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@ -934,6 +936,144 @@
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};
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ufsphy_mem: ufsphy_mem@1d87000 {
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reg = <0x1d87000 0xda8>; /* PHY regs */
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reg-names = "phy_mem";
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#phy-cells = <0>;
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lanes-per-direction = <2>;
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clock-names = "ref_clk_src",
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"ref_clk",
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"ref_aux_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_MEM_CLKREF_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufshc_mem 0>;
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status = "disabled";
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};
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ufshc_mem: ufshc@1d84000 {
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compatible = "qcom,ufshc";
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reg = <0x1d84000 0x2500>,
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<0x1d90000 0x8000>;
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reg-names = "ufs_mem", "ufs_ice";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy_mem>;
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phy-names = "ufsphy";
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#reset-cells = <1>;
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lanes-per-direction = <2>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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qcom,ufs-bus-bw,name = "ufshc_mem";
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qcom,ufs-bus-bw,num-cases = <26>;
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qcom,ufs-bus-bw,num-paths = <2>;
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qcom,ufs-bus-bw,vectors-KBps =
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/*
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* During HS G3 UFS runs at nominal voltage corner, vote
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* higher bandwidth to push other buses in the data path
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* to run at nominal to achieve max throughput.
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* 4GBps pushes BIMC to run at nominal.
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* 200MBps pushes CNOC to run at nominal.
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* Vote for half of this bandwidth for HS G3 1-lane.
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* For max bandwidth, vote high enough to push the buses
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* to run in turbo voltage corner.
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*/
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<0 0>, <0 0>, /* No vote */
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<922 0>, <1000 0>, /* PWM G1 */
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<1844 0>, <1000 0>, /* PWM G2 */
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<3688 0>, <1000 0>, /* PWM G3 */
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<7376 0>, <1000 0>, /* PWM G4 */
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<1844 0>, <1000 0>, /* PWM G1 L2 */
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<3688 0>, <1000 0>, /* PWM G2 L2 */
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<7376 0>, <1000 0>, /* PWM G3 L2 */
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<14752 0>, <1000 0>, /* PWM G4 L2 */
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<127796 0>, <1000 0>, /* HS G1 RA */
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<255591 0>, <1000 0>, /* HS G2 RA */
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<2097152 0>, <102400 0>, /* HS G3 RA */
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<4194304 0>, <204800 0>, /* HS G4 RA */
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<255591 0>, <1000 0>, /* HS G1 RA L2 */
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<511181 0>, <1000 0>, /* HS G2 RA L2 */
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<4194304 0>, <204800 0>, /* HS G3 RA L2 */
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<8388608 0>, <409600 0>, /* HS G4 RA L2 */
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<149422 0>, <1000 0>, /* HS G1 RB */
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<298189 0>, <1000 0>, /* HS G2 RB */
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<2097152 0>, <102400 0>, /* HS G3 RB */
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<4194304 0>, <204800 0>, /* HS G4 RB */
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<298189 0>, <1000 0>, /* HS G1 RB L2 */
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<596378 0>, <1000 0>, /* HS G2 RB L2 */
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/* As UFS working in HS G3 RB L2 mode, aggregated
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* bandwidth (AB) should take care of providing
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* optimum throughput requested. However, as tested,
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* in order to scale up CNOC clock, instantaneous
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* bindwidth (IB) needs to be given a proper value too.
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*/
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<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
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<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
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<7643136 0>, <307200 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
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"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
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"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
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"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
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"MAX";
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reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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status = "disabled";
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qos0 {
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mask = <0xf0>;
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vote = <44>;
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};
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qos1 {
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mask = <0x0f>;
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vote = <44>;
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};
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x00ac0000 0x6000>;
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