A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Add support for performance lock on HOLI"

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qctecmdr 2020-09-01 17:18:52 -07:00 • committed by Gerrit - the friendly Code Review server
commit 28c4e26499
2 changed files with 13 additions and 2 deletions
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8
bindings/cpufreq/cpufreq-qcom-hw.txt
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@ -42,6 +42,14 @@ Properties:
Definition: Indicate to check for Enable of FW before registering
with cpufreq.
- qcom,perf-lock-support
Usage: Optional
Value type: bool
Definition: Indicate to check for performance lock support in FW.
In case this property is present, the reg & reg-names
should have the "pdmem-domainX" to indicate the
corresponding bases.
* Property qcom,freq-domain
Devices supporting freq-domain must set their "qcom,freq-domain" property with
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

7
qcom/holi.dtsi
View file

@ -1227,13 +1227,16 @@
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>,
<0x0fd04504 0x4>, <0x0fd04508 0x4>;
reg-names = "freq-domain0", "freq-domain1",
"pdmem-domain0", "pdmem-domain1";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,max-lut-entries = <12>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";