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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
msm: kgsl: Get rid of gmu_core_snapshot and gmu_core_dev_snapshot
Assign the gmu specific snapshot function to gpudev->snapshot instead of creating a gmu_core_snapshot. This function will send an nmi if we hit a gmu fault. Then, it will capture gmu snapshot followed by the generic a6xx_snapshot as against a6xx snapshot calling the gmu snapshot. Do the same for rgmu. This helps get rid of gmu_core_snapshot and gmu_core_dev_snapshot() functions. Change-Id: I0f72a930633557260b59a76f0161bcde8c5a6da2 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt
parent
efa44eb2e6
commit
2960707394
13 changed files with 94 additions and 113 deletions
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@ -1877,4 +1877,12 @@ void adreno_get_bus_counters(struct adreno_device *adreno_dev);
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* power up the gpu
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*/
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void adreno_clear_dcvs_counters(struct adreno_device *adreno_dev);
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/**
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* gmu_fault_snapshot - Set gmu fault and trigger snapshot
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* @device: Pointer to the kgsl device
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*
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* Set the gmu fault and take snapshot when we hit a gmu fault
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*/
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void gmu_fault_snapshot(struct kgsl_device *device);
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#endif /*__ADRENO_H */
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@ -2654,7 +2654,7 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
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.reg_offsets = a6xx_register_offsets,
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.probe = a6xx_gmu_device_probe,
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.start = a6xx_start,
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.snapshot = a6xx_snapshot,
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.snapshot = a6xx_gmu_snapshot,
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.init = a6xx_init,
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.irq_handler = a6xx_irq_handler,
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.rb_start = a6xx_rb_start,
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@ -2689,7 +2689,7 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
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.reg_offsets = a6xx_register_offsets,
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.probe = a6xx_rgmu_device_probe,
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.start = a6xx_start,
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.snapshot = a6xx_snapshot,
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.snapshot = a6xx_rgmu_snapshot,
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.init = a6xx_init,
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.irq_handler = a6xx_irq_handler,
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.rb_start = a6xx_rb_start,
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@ -2724,7 +2724,7 @@ struct adreno_gpudev adreno_a630_gpudev = {
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.reg_offsets = a6xx_register_offsets,
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.probe = a6xx_gmu_device_probe,
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.start = a6xx_start,
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.snapshot = a6xx_snapshot,
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.snapshot = a6xx_gmu_snapshot,
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.init = a6xx_init,
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.irq_handler = a6xx_irq_handler,
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.rb_start = a6xx_rb_start,
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@ -102,6 +102,12 @@ static struct gmu_iommu_context a6xx_gmu_ctx[] = {
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[GMU_CONTEXT_KERNEL] = { .name = "gmu_kernel" }
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};
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void gmu_fault_snapshot(struct kgsl_device *device)
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{
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device->gmu_fault = true;
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kgsl_device_snapshot(device, NULL, true);
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}
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struct a6xx_gmu_device *to_a6xx_gmu(struct adreno_device *adreno_dev)
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{
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struct a6xx_device *a6xx_dev = container_of(adreno_dev,
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@ -443,8 +449,7 @@ static int a6xx_gmu_device_start(struct adreno_device *adreno_dev)
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gmu_core_regread(device,
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A6XX_GMU_CM3_DTCM_START + (0x3fdc >> 2), &val);
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dev_err(&gmu->pdev->dev, "GMU doesn't boot: 0x%x\n", val);
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a6xx_gmu_snapshot(device);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -468,7 +473,7 @@ static int a6xx_gmu_hfi_start(struct adreno_device *adreno_dev)
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GMU_START_TIMEOUT,
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BIT(0))) {
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dev_err(&gmu->pdev->dev, "GMU HFI init failed\n");
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a6xx_gmu_snapshot(device);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -744,8 +749,8 @@ static int a6xx_gmu_oob_set(struct kgsl_device *device,
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if (timed_poll_check(device, A6XX_GMU_GMU2HOST_INTR_INFO, check,
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GPU_START_TIMEOUT, check)) {
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gmu_fault_snapshot(device);
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ret = -ETIMEDOUT;
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a6xx_gmu_snapshot(device);
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WARN(1, "OOB request %s timed out\n", oob_to_str(req));
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}
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@ -914,7 +919,7 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev)
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SPTPRAC_CTRL_TIMEOUT,
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SPTPRAC_POWERON_STATUS_MASK)) {
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dev_err(&gmu->pdev->dev, "power on SPTPRAC fail\n");
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a6xx_gmu_snapshot(device);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -1112,6 +1117,7 @@ static int a6xx_gmu_wait_for_lowest_idle(struct adreno_device *adreno_dev)
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}
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WARN_ON(1);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -1133,6 +1139,7 @@ static int a6xx_gmu_wait_for_idle(struct adreno_device *adreno_dev)
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"GMU not idling: status2=0x%x %llx %llx\n",
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status2, ts1,
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a6xx_read_alwayson(ADRENO_DEVICE(device)));
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -1936,14 +1943,13 @@ static irqreturn_t a6xx_gmu_irq_handler(int irq, void *data)
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return IRQ_HANDLED;
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}
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void a6xx_gmu_snapshot(struct kgsl_device *device)
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static void a6xx_gmu_nmi(struct adreno_device *adreno_dev)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
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/* Abstain from sending another nmi or over-writing snapshot */
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if (device->gmu_fault)
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/* No need to nmi if it was a gpu fault */
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if (!device->gmu_fault)
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return;
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/* make sure we're reading the latest cm3_fault */
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@ -1960,16 +1966,24 @@ void a6xx_gmu_snapshot(struct kgsl_device *device)
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/* Wait for the NMI to be handled */
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udelay(100);
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}
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}
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kgsl_device_snapshot(device, NULL, true);
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void a6xx_gmu_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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a6xx_gmu_nmi(adreno_dev);
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a6xx_gmu_device_snapshot(device, snapshot);
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a6xx_snapshot(adreno_dev, snapshot);
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR,
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0xffffffff);
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK,
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HFI_IRQ_MASK);
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device->gmu_fault = true;
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}
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static int a6xx_gmu_aop_send_acd_state(struct mbox_chan *channel, bool flag)
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@ -2245,14 +2259,9 @@ static struct gmu_dev_ops a6xx_gmudev = {
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.gx_is_on = a6xx_gmu_gx_is_on,
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.ifpc_store = a6xx_gmu_ifpc_store,
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.ifpc_show = a6xx_gmu_ifpc_show,
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.snapshot = a6xx_gmu_device_snapshot,
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.cooperative_reset = a6xx_gmu_cooperative_reset,
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.wait_for_active_transition = a6xx_gmu_wait_for_active_transition,
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.scales_bandwidth = a6xx_gmu_scales_bandwidth,
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};
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static struct gmu_core_ops a6xx_gmu_ops = {
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.snapshot = a6xx_gmu_snapshot,
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.acd_set = a6xx_gmu_acd_set,
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};
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@ -2592,7 +2601,6 @@ static int a6xx_gmu_probe(struct kgsl_device *device,
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set_bit(GMU_ENABLED, &device->gmu_core.flags);
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device->gmu_core.core_ops = &a6xx_gmu_ops;
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device->gmu_core.dev_ops = &a6xx_gmudev;
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/* Initialize HFI and GMU interrupts */
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@ -286,9 +286,13 @@ void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev);
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void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev);
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/**
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* a6xx_gmu_snapshot - Send nmi to gmu and take snapshot
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* @device: Pointer to the kgsl device
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* a6xx_gmu_snapshot- Take snapshot for gmu targets
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* @adreno_dev: Pointer to the adreno device
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* @snapshot: Pointer to the snapshot structure
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*
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* Send an NMI to gmu if we hit a gmu fault. Then take gmu
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* snapshot and carry on with rest of the a6xx snapshot
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*/
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void a6xx_gmu_snapshot(struct kgsl_device *device);
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void a6xx_gmu_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot);
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#endif
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@ -245,6 +245,7 @@ static int receive_ack_cmd(struct a6xx_gmu_device *gmu, void *rcvd,
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struct pending_cmd *ret_cmd)
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{
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struct adreno_device *adreno_dev = a6xx_gmu_to_adreno(gmu);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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uint32_t *ack = rcvd;
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uint32_t hdr = ack[0];
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uint32_t req_hdr = ack[1];
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@ -266,7 +267,7 @@ static int receive_ack_cmd(struct a6xx_gmu_device *gmu, void *rcvd,
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"HFI ACK: Cannot find sender for 0x%8.8x Waiter: 0x%8.8x\n",
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req_hdr, ret_cmd->sent_hdr);
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a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
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gmu_fault_snapshot(device);
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return -ENODEV;
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}
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@ -310,6 +311,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
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uint32_t queue_idx, void *data, struct pending_cmd *ret_cmd)
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{
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struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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int rc;
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uint32_t *cmd = data;
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struct a6xx_hfi *hfi = &gmu->hfi;
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@ -329,7 +331,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
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HFI_IRQ_MSGQ_MASK, HFI_IRQ_MSGQ_MASK, HFI_RSP_TIMEOUT);
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if (rc) {
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a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
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gmu_fault_snapshot(device);
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dev_err(&gmu->pdev->dev,
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"Timed out waiting on ack for 0x%8.8x (id %d, sequence %d)\n",
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cmd[0], MSG_HDR_GET_ID(*cmd), MSG_HDR_GET_SEQNUM(*cmd));
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@ -337,7 +339,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
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}
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/* Clear the interrupt */
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gmu_core_regwrite(KGSL_DEVICE(adreno_dev), A6XX_GMU_GMU2HOST_INTR_CLR,
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR,
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HFI_IRQ_MSGQ_MASK);
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rc = a6xx_hfi_process_queue(gmu, HFI_MSG_ID, ret_cmd);
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@ -359,8 +361,9 @@ static int a6xx_hfi_send_generic_req(struct adreno_device *adreno_dev,
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if (!rc && ret_cmd.results[2] == HFI_ACK_ERROR) {
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struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
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gmu_fault_snapshot(device);
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dev_err(&gmu->pdev->dev, "HFI ACK failure: Req 0x%8.8X\n",
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ret_cmd.results[1]);
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return -EINVAL;
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@ -375,7 +375,7 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev)
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err:
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/* If fenced write fails, take inline snapshot and trigger recovery */
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if (!in_interrupt()) {
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gmu_core_snapshot(device);
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gmu_fault_snapshot(device);
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adreno_set_gpu_fault(adreno_dev,
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ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
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} else {
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@ -42,8 +42,6 @@ static const unsigned int a6xx_rgmu_registers[] = {
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0x26000, 0x26002,
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};
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static void a6xx_rgmu_snapshot(struct kgsl_device *device);
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static struct a6xx_rgmu_device *to_a6xx_rgmu(struct adreno_device *adreno_dev)
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{
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struct a6xx_device *a6xx_dev = container_of(adreno_dev,
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@ -167,7 +165,7 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device,
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dev_err(&rgmu->pdev->dev,
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"Timed out while setting OOB req:%s status:0x%x\n",
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oob_to_str(req), status);
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a6xx_rgmu_snapshot(device);
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gmu_fault_snapshot(device);
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return ret;
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}
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@ -368,7 +366,7 @@ static int a6xx_rgmu_wait_for_lowest_idle(struct adreno_device *adreno_dev)
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reg[7], reg[8], reg[9]);
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WARN_ON(1);
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a6xx_rgmu_snapshot(device);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -452,7 +450,7 @@ static int a6xx_rgmu_fw_start(struct adreno_device *adreno_dev,
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gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, &status);
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dev_err(&rgmu->pdev->dev,
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"rgmu boot Failed. status:%08x\n", status);
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a6xx_rgmu_snapshot(device);
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gmu_fault_snapshot(device);
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return -ETIMEDOUT;
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}
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@ -522,35 +520,29 @@ static int a6xx_rgmu_disable_gdsc(struct adreno_device *adreno_dev)
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static void a6xx_rgmu_halt_execution(struct kgsl_device *device);
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static void a6xx_rgmu_snapshot(struct kgsl_device *device)
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void a6xx_rgmu_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(adreno_dev);
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if (device->gmu_fault)
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return;
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/* Mask so there's no interrupt caused by NMI */
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
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/* Make sure the interrupt is masked */
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wmb();
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/*
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* Halt RGMU execution so that GX will not
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* be collapsed while dumping snapshot.
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*/
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a6xx_rgmu_halt_execution(device);
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kgsl_device_snapshot(device, NULL, true);
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adreno_snapshot_registers(device, snapshot, a6xx_rgmu_registers,
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ARRAY_SIZE(a6xx_rgmu_registers) / 2);
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a6xx_snapshot(adreno_dev, snapshot);
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff);
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK,
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RGMU_OOB_IRQ_MASK);
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rgmu->fault_count++;
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device->gmu_fault = true;
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if (device->gmu_fault)
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rgmu->fault_count++;
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}
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static void a6xx_rgmu_suspend(struct adreno_device *adreno_dev)
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@ -644,6 +636,15 @@ static void a6xx_rgmu_halt_execution(struct kgsl_device *device)
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struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(ADRENO_DEVICE(device));
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unsigned int index, status, fence;
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if (!device->gmu_fault)
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return;
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/* Mask so there's no interrupt caused by NMI */
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gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
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/* Make sure the interrupt is masked */
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wmb();
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gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, &index);
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gmu_core_regread(device, A6XX_RGMU_CX_PCC_STATUS, &status);
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gmu_core_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &fence);
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@ -666,22 +667,6 @@ static void a6xx_rgmu_halt_execution(struct kgsl_device *device)
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}
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/*
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* a6xx_rgmu_snapshot() - A6XX GMU snapshot function
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* @adreno_dev: Device being snapshotted
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* @snapshot: Pointer to the snapshot instance
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*
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* This is where all of the A6XX GMU specific bits and pieces are grabbed
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* into the snapshot memory
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*/
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||||
static void a6xx_rgmu_device_snapshot(struct kgsl_device *device,
|
||||
struct kgsl_snapshot *snapshot)
|
||||
{
|
||||
|
||||
adreno_snapshot_registers(device, snapshot, a6xx_rgmu_registers,
|
||||
ARRAY_SIZE(a6xx_rgmu_registers) / 2);
|
||||
}
|
||||
|
||||
static void halt_gbif_arb(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -1174,11 +1159,6 @@ static struct gmu_dev_ops a6xx_rgmudev = {
|
|||
.gx_is_on = a6xx_rgmu_gx_is_on,
|
||||
.ifpc_store = a6xx_rgmu_ifpc_store,
|
||||
.ifpc_show = a6xx_rgmu_ifpc_show,
|
||||
.snapshot = a6xx_rgmu_device_snapshot,
|
||||
};
|
||||
|
||||
static struct gmu_core_ops a6xx_rgmu_ops = {
|
||||
.snapshot = a6xx_rgmu_snapshot,
|
||||
};
|
||||
|
||||
static int a6xx_rgmu_irq_probe(struct kgsl_device *device)
|
||||
|
|
@ -1345,7 +1325,6 @@ static int a6xx_rgmu_probe(struct kgsl_device *device,
|
|||
rgmu->idle_level = GPU_HW_ACTIVE;
|
||||
|
||||
set_bit(GMU_ENABLED, &device->gmu_core.flags);
|
||||
device->gmu_core.core_ops = &a6xx_rgmu_ops;
|
||||
device->gmu_core.dev_ops = &a6xx_rgmudev;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -78,4 +78,15 @@ int a6xx_rgmu_device_probe(struct platform_device *pdev,
|
|||
* Return: 0 on success or negative error on failure
|
||||
*/
|
||||
int a6xx_rgmu_restart(struct kgsl_device *device);
|
||||
|
||||
/**
|
||||
* a6xx_rgmu_snapshot - Take snapshot for rgmu based targets
|
||||
* @adreno_dev: Pointer to the adreno device
|
||||
* @snapshot: Pointer to the snapshot
|
||||
*
|
||||
* This function halts rgmu execution if we hit a rgmu
|
||||
* fault. And then, it takes rgmu and gpu snapshot.
|
||||
*/
|
||||
void a6xx_rgmu_snapshot(struct adreno_device *adreno_dev,
|
||||
struct kgsl_snapshot *snapshot);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1784,9 +1784,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
|
|||
unsigned int i, roq_size;
|
||||
u32 hi, lo;
|
||||
|
||||
/* GMU TCM data dumped through AHB */
|
||||
gmu_core_dev_snapshot(device, snapshot);
|
||||
|
||||
/*
|
||||
* Dump debugbus data here to capture it for both
|
||||
* GMU and GPU snapshot. Debugbus data can be accessed
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ static void adreno_ringbuffer_wptr(struct adreno_device *adreno_dev,
|
|||
* If WPTR update fails, take inline snapshot and trigger
|
||||
* recovery.
|
||||
*/
|
||||
gmu_core_snapshot(device);
|
||||
gmu_fault_snapshot(device);
|
||||
adreno_set_gpu_fault(adreno_dev,
|
||||
ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
|
||||
adreno_dispatcher_schedule(device);
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ static bool _acd_show(struct adreno_device *adreno_dev)
|
|||
|
||||
static int _acd_store(struct adreno_device *adreno_dev, bool val)
|
||||
{
|
||||
return gmu_core_acd_set(KGSL_DEVICE(adreno_dev), val);
|
||||
return gmu_core_dev_acd_set(KGSL_DEVICE(adreno_dev), val);
|
||||
}
|
||||
|
||||
static ssize_t _sysfs_store_u32(struct device *dev,
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ bool gmu_core_isenabled(struct kgsl_device *device)
|
|||
|
||||
bool gmu_core_gpmu_isenabled(struct kgsl_device *device)
|
||||
{
|
||||
return (device->gmu_core.core_ops != NULL);
|
||||
return (device->gmu_core.dev_ops != NULL);
|
||||
}
|
||||
|
||||
bool gmu_core_scales_bandwidth(struct kgsl_device *device)
|
||||
|
|
@ -64,20 +64,12 @@ bool gmu_core_scales_bandwidth(struct kgsl_device *device)
|
|||
return false;
|
||||
}
|
||||
|
||||
void gmu_core_snapshot(struct kgsl_device *device)
|
||||
int gmu_core_dev_acd_set(struct kgsl_device *device, bool val)
|
||||
{
|
||||
struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device);
|
||||
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
|
||||
|
||||
if (gmu_core_ops && gmu_core_ops->snapshot)
|
||||
gmu_core_ops->snapshot(device);
|
||||
}
|
||||
|
||||
int gmu_core_acd_set(struct kgsl_device *device, bool val)
|
||||
{
|
||||
struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device);
|
||||
|
||||
if (gmu_core_ops && gmu_core_ops->acd_set)
|
||||
return gmu_core_ops->acd_set(device, val);
|
||||
if (ops && ops->acd_set)
|
||||
return ops->acd_set(device, val);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -182,15 +174,6 @@ void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req)
|
|||
ops->oob_clear(device, req);
|
||||
}
|
||||
|
||||
void gmu_core_dev_snapshot(struct kgsl_device *device,
|
||||
struct kgsl_snapshot *snapshot)
|
||||
{
|
||||
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
|
||||
|
||||
if (ops && ops->snapshot)
|
||||
ops->snapshot(device, snapshot);
|
||||
}
|
||||
|
||||
void gmu_core_dev_cooperative_reset(struct kgsl_device *device)
|
||||
{
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@
|
|||
|
||||
/* GMU_DEVICE - Given an KGSL device return the GMU specific struct */
|
||||
#define GMU_DEVICE_OPS(_a) ((_a)->gmu_core.dev_ops)
|
||||
#define GMU_CORE_OPS(_a) ((_a)->gmu_core.core_ops)
|
||||
|
||||
#define NUM_BW_LEVELS 100
|
||||
#define MAX_GX_LEVELS 16
|
||||
|
|
@ -100,23 +99,17 @@ struct device_node;
|
|||
struct kgsl_device;
|
||||
struct kgsl_snapshot;
|
||||
|
||||
struct gmu_core_ops {
|
||||
void (*snapshot)(struct kgsl_device *device);
|
||||
int (*acd_set)(struct kgsl_device *device, bool val);
|
||||
};
|
||||
|
||||
struct gmu_dev_ops {
|
||||
int (*oob_set)(struct kgsl_device *device, enum oob_request req);
|
||||
void (*oob_clear)(struct kgsl_device *device, enum oob_request req);
|
||||
bool (*gx_is_on)(struct kgsl_device *device);
|
||||
int (*ifpc_store)(struct kgsl_device *device, unsigned int val);
|
||||
unsigned int (*ifpc_show)(struct kgsl_device *device);
|
||||
void (*snapshot)(struct kgsl_device *device,
|
||||
struct kgsl_snapshot *shapshot);
|
||||
void (*cooperative_reset)(struct kgsl_device *device);
|
||||
void (*halt_execution)(struct kgsl_device *device);
|
||||
int (*wait_for_active_transition)(struct kgsl_device *device);
|
||||
bool (*scales_bandwidth)(struct kgsl_device *device);
|
||||
int (*acd_set)(struct kgsl_device *device, bool val);
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -127,7 +120,6 @@ struct gmu_dev_ops {
|
|||
* gmu registers using offset defined in GPU register space.
|
||||
* @reg_len: GMU registers length
|
||||
* @reg_virt: GMU CSR virtual address
|
||||
* @core_ops: Pointer to gmu core operations
|
||||
* @dev_ops: Pointer to gmu device operations
|
||||
* @flags: GMU flags
|
||||
*/
|
||||
|
|
@ -136,7 +128,6 @@ struct gmu_core_device {
|
|||
unsigned int gmu2gpu_offset;
|
||||
unsigned int reg_len;
|
||||
void __iomem *reg_virt;
|
||||
struct gmu_core_ops *core_ops;
|
||||
struct gmu_dev_ops *dev_ops;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
|
@ -149,11 +140,10 @@ extern struct platform_driver a6xx_rgmu_driver;
|
|||
void __init gmu_core_register(void);
|
||||
void __exit gmu_core_unregister(void);
|
||||
|
||||
void gmu_core_snapshot(struct kgsl_device *device);
|
||||
bool gmu_core_gpmu_isenabled(struct kgsl_device *device);
|
||||
bool gmu_core_scales_bandwidth(struct kgsl_device *device);
|
||||
bool gmu_core_isenabled(struct kgsl_device *device);
|
||||
int gmu_core_acd_set(struct kgsl_device *device, bool val);
|
||||
int gmu_core_dev_acd_set(struct kgsl_device *device, bool val);
|
||||
bool gmu_core_is_register_offset(struct kgsl_device *device,
|
||||
unsigned int offsetwords);
|
||||
void gmu_core_regread(struct kgsl_device *device, unsigned int offsetwords,
|
||||
|
|
@ -179,8 +169,6 @@ void gmu_core_regrmw(struct kgsl_device *device, unsigned int offsetwords,
|
|||
unsigned int mask, unsigned int bits);
|
||||
int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req);
|
||||
void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req);
|
||||
void gmu_core_dev_snapshot(struct kgsl_device *device,
|
||||
struct kgsl_snapshot *snapshot);
|
||||
bool gmu_core_dev_gx_is_on(struct kgsl_device *device);
|
||||
int gmu_core_dev_ifpc_show(struct kgsl_device *device);
|
||||
int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val);
|
||||
|
|
|
|||
Loading…
Reference in a new issue