display/holi: support the configuration of strength offset in each projects

The clock and data lanes have a calibration circuitry feature. To offset the drive
strength from the calibrated value in an increasing or decreasing manner, use 6 bit
two’s complement values.
For some project ,will change the strength offset to reduce the mipi voltage, to fix
rf desense issue.

By default, there are only two bytes to config the strength of lane.
Support the configuration of strength offset in each projects, we must expand to 4 bytes.
And the default value is 0.

Change-Id: Ifaa2a0024b10176c638d4bc44756f9d09a1927ef
Signed-off-by: houdz1 <houdz1@lenovo.com>
Reviewed-on: https://gerrit.mot.com/1852325
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Yeqing Wang <wangyq13@motorola.com>
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
houdz1 2021-01-15 16:30:57 +08:00 • committed by panyq6
commit 2a1379fdfd

View file

@ -584,3 +584,11 @@
&ufshc_mem {
spm-level = <3>;
};
&mdss_dsi_phy0 {
qcom,platform-strength-ctrl = [55 03 00 00
55 03 00 00
55 03 00 00
55 03 00 00
55 00 00 00];
};