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msm: kgsl: Fix gmu fence error during slumber

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There can exist a race where we clear the A6XX_RBBM_INT_0_MASK
register while the gpu is going into IFPC. Fix this by clearing this
register before clearing the OOB.

Change-Id: I08e9dbccbfdbee93ba7ef35fbbc673938ee033da
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt 2020-08-12 14:35:11 -06:00
commit 2b2f29cc50
2 changed files with 6 additions and 2 deletions
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4
drivers/gpu/msm/adreno_a6xx_gmu.c
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@ -3069,10 +3069,12 @@ static int a6xx_power_off(struct adreno_device *adreno_dev)
if (adreno_is_a630(adreno_dev))
a630_vbif_halt(adreno_dev);
adreno_irqctrl(adreno_dev, 0);
a6xx_gmu_oob_clear(device, oob_gpu);
no_gx_power:
a6xx_disable_gpu_irq(adreno_dev);
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
a6xx_gmu_power_off(adreno_dev);

4
drivers/gpu/msm/adreno_a6xx_rgmu.c
View file

@ -1056,6 +1056,8 @@ static int a6xx_power_off(struct adreno_device *adreno_dev)
/* Save physical performance counter values before GPU power down*/
adreno_perfcounter_save(adreno_dev);
adreno_irqctrl(adreno_dev, 0);
a6xx_rgmu_prepare_stop(device);
a6xx_rgmu_oob_clear(device, oob_gpu);
@ -1067,7 +1069,7 @@ no_gx_power:
adreno_wait_for_halt_ack(device, ADRENO_REG_GBIF_HALT_ACK,
A6XX_GBIF_CLIENT_HALT_MASK);
a6xx_disable_gpu_irq(adreno_dev);
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
a6xx_rgmu_power_off(adreno_dev);