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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "bindings: clock: qcom: Update the GPU CC clock IDs"
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qctecmdr
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commit
2f20b6b85e
3 changed files with 86 additions and 33 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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@ -11,6 +11,7 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/clk/qcom.h>
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#include "clk-branch.h"
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#include "clk-debug.h"
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@ -199,6 +200,10 @@ static void clk_branch2_init(struct clk_hw *hw)
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}
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const struct clk_ops clk_branch2_ops = {
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.prepare = clk_prepare_regmap,
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.unprepare = clk_unprepare_regmap,
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.pre_rate_change = clk_pre_change_regmap,
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.post_rate_change = clk_post_change_regmap,
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.enable = clk_branch2_enable,
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.disable = clk_branch2_disable,
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.is_enabled = clk_is_enabled_regmap,
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@ -272,3 +277,55 @@ const struct clk_ops clk_branch_simple_ops = {
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
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int qcom_clk_set_flags(struct clk *clk, unsigned long flags)
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{
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struct clk_hw *hw;
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struct clk_branch *br;
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u32 cbcr_val = 0, cbcr_mask;
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int ret;
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if (IS_ERR_OR_NULL(clk))
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return 0;
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hw = __clk_get_hw(clk);
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if (IS_ERR_OR_NULL(hw))
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return -EINVAL;
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switch (flags) {
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case CLKFLAG_PERIPH_OFF_SET:
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cbcr_val = cbcr_mask = BIT(12);
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break;
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case CLKFLAG_PERIPH_OFF_CLEAR:
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cbcr_mask = BIT(12);
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break;
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case CLKFLAG_RETAIN_PERIPH:
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cbcr_val = cbcr_mask = BIT(13);
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break;
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case CLKFLAG_NORETAIN_PERIPH:
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cbcr_mask = BIT(13);
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break;
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case CLKFLAG_RETAIN_MEM:
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cbcr_val = cbcr_mask = BIT(14);
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break;
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case CLKFLAG_NORETAIN_MEM:
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cbcr_mask = BIT(14);
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break;
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default:
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return -EINVAL;
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}
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br = to_clk_branch(hw);
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ret = regmap_update_bits(br->clkr.regmap, br->halt_reg, cbcr_mask,
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cbcr_val);
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if (ret)
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return ret;
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/* Make sure power is enabled/disabled before returning. */
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mb();
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udelay(1);
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return 0;
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}
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EXPORT_SYMBOL(qcom_clk_set_flags);
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@ -7,38 +7,24 @@
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_HOLI_H
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/* GPU_CC clocks */
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL1 1
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#define GPU_CC_ACD_AHB_CLK 2
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#define GPU_CC_ACD_CXO_CLK 3
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#define GPU_CC_AHB_CLK 4
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#define GPU_CC_CRC_AHB_CLK 5
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#define GPU_CC_CX_APB_CLK 6
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#define GPU_CC_CX_GFX3D_CLK 7
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#define GPU_CC_CX_GFX3D_SLV_CLK 8
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#define GPU_CC_CX_GMU_CLK 9
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#define GPU_CC_CX_SNOC_DVM_CLK 10
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#define GPU_CC_CXO_AON_CLK 11
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#define GPU_CC_CXO_CLK 12
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#define GPU_CC_GMU_CLK_SRC 13
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#define GPU_CC_GX_CXO_CLK 14
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#define GPU_CC_GX_GFX3D_CLK 15
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#define GPU_CC_GX_GMU_CLK 16
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#define GPU_CC_GX_QDSS_TSCTR_CLK 17
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#define GPU_CC_GX_VSENSE_CLK 18
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#define GPU_CC_SLEEP_CLK 19
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL1 1
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#define GPU_CC_AHB_CLK 2
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#define GPU_CC_CX_GFX3D_CLK 3
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#define GPU_CC_CX_GFX3D_SLV_CLK 4
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#define GPU_CC_CX_GMU_CLK 5
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#define GPU_CC_CX_SNOC_DVM_CLK 6
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#define GPU_CC_CXO_AON_CLK 7
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#define GPU_CC_CXO_CLK 8
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#define GPU_CC_GMU_CLK_SRC 9
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#define GPU_CC_GX_CXO_CLK 10
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#define GPU_CC_GX_GFX3D_CLK 11
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#define GPU_CC_GX_GFX3D_CLK_SRC 12
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#define GPU_CC_GX_GMU_CLK 13
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#define GPU_CC_SLEEP_CLK 14
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/* GPU_CC power domains */
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#define CX_GDSC 0
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#define GX_GDSC 1
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/* GPU_CC resets */
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#define GPUCC_GPU_CC_ACD_BCR 0
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#define GPUCC_GPU_CC_CX_BCR 1
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 2
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#define GPUCC_GPU_CC_GMU_BCR 3
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#define GPUCC_GPU_CC_GX_BCR 4
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#define GPUCC_GPU_CC_RBCPR_BCR 5
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#define GPUCC_GPU_CC_XO_BCR 6
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#define CX_GDSC 0
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#define GX_GDSC 1
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#endif
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef __LINUX_CLK_QCOM_H_
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@ -8,6 +8,16 @@
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#include <linux/clk-provider.h>
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enum branch_mem_flags {
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CLKFLAG_RETAIN_PERIPH,
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CLKFLAG_NORETAIN_PERIPH,
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CLKFLAG_RETAIN_MEM,
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CLKFLAG_NORETAIN_MEM,
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CLKFLAG_PERIPH_OFF_SET,
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CLKFLAG_PERIPH_OFF_CLEAR,
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};
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int qcom_clk_get_voltage(struct clk *clk, unsigned long rate);
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int qcom_clk_set_flags(struct clk *clk, unsigned long flags);
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#endif /* __LINUX_CLK_QCOM_H_ */
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