A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Add iommu and h/w reset support for yupik"

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qctecmdr 2021-01-10 22:44:56 -08:00 • committed by Gerrit - the friendly Code Review server
commit 30fc64a262
1 changed files with 14 additions and 0 deletions
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14
qcom/yupik.dtsi
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@ -2546,6 +2546,10 @@
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",
"cqhci_ice_hwkm";
iommus = <&apps_smmu 0xc0 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
@ -2591,6 +2595,8 @@
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
@ -2598,6 +2604,10 @@
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
@ -2616,6 +2626,10 @@
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
iommus = <&apps_smmu 0x100 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";