mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 00:00:00 -04:00
Merge "ARM: dts: msm: add initial PHY sequence for PCIe0 and PCIe1 on lahaina"
This commit is contained in:
commit
329489d312
1 changed files with 139 additions and 8 deletions
|
|
@ -68,15 +68,23 @@
|
|||
<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,
|
||||
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
|
||||
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
|
||||
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
|
||||
<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
|
||||
<&clock_gcc PCIE_0_PIPE_CLK>;
|
||||
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
|
||||
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
|
||||
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
|
||||
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
|
||||
"pcie_tbu_clk", "pcie_phy_refgen_clk",
|
||||
"pcie_ddrss_sf_tbu_clk";
|
||||
"pcie_ddrss_sf_tbu_clk",
|
||||
"pcie_aggre_noc_0_axi_clk",
|
||||
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>;
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>,
|
||||
<0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&clock_gcc GCC_PCIE_0_BCR>,
|
||||
<&clock_gcc GCC_PCIE_0_PHY_BCR>;
|
||||
|
|
@ -102,7 +110,58 @@
|
|||
qcom,phy-status-offset = <0x214>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x240>;
|
||||
qcom,phy-sequence = <0 0 0>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x0094 0x08 0x0
|
||||
0x0154 0x34 0x0
|
||||
0x016c 0x08 0x0
|
||||
0x0058 0x0f 0x0
|
||||
0x00a4 0x42 0x0
|
||||
0x0110 0x24 0x0
|
||||
0x011c 0x03 0x0
|
||||
0x0118 0xb4 0x0
|
||||
0x010c 0x02 0x0
|
||||
0x01bc 0x11 0x0
|
||||
0x00bc 0x82 0x0
|
||||
0x00d4 0x03 0x0
|
||||
0x00d0 0x55 0x0
|
||||
0x00cc 0x55 0x0
|
||||
0x00b0 0x1a 0x0
|
||||
0x00ac 0x0a 0x0
|
||||
0x00c4 0x68 0x0
|
||||
0x00e0 0x02 0x0
|
||||
0x00dc 0xaa 0x0
|
||||
0x00d8 0xab 0x0
|
||||
0x00b8 0x34 0x0
|
||||
0x00b4 0x14 0x0
|
||||
0x0158 0x01 0x0
|
||||
0x0074 0x06 0x0
|
||||
0x007c 0x16 0x0
|
||||
0x0084 0x36 0x0
|
||||
0x0078 0x06 0x0
|
||||
0x0080 0x16 0x0
|
||||
0x0088 0x36 0x0
|
||||
0x01b0 0x1e 0x0
|
||||
0x01ac 0xb9 0x0
|
||||
0x01b8 0x18 0x0
|
||||
0x01b4 0x94 0x0
|
||||
0x0050 0x07 0x0
|
||||
0x0010 0x00 0x0
|
||||
0x001c 0x31 0x0
|
||||
0x0020 0x01 0x0
|
||||
0x0024 0xde 0x0
|
||||
0x0028 0x07 0x0
|
||||
0x0030 0x4c 0x0
|
||||
0x0034 0x06 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x0654 0x00 0x0
|
||||
0x06a8 0x0f 0x0
|
||||
0x0048 0x90 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0388 0x88 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x02dc 0x0d 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -215,15 +274,21 @@
|
|||
<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
||||
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,
|
||||
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
|
||||
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
|
||||
<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
||||
<&clock_gcc PCIE_1_PIPE_CLK>;
|
||||
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
|
||||
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
|
||||
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
|
||||
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
|
||||
"pcie_tbu_clk", "pcie_phy_refgen_clk",
|
||||
"pcie_ddrss_sf_tbu_clk";
|
||||
"pcie_ddrss_sf_tbu_clk",
|
||||
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>;
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>,
|
||||
<0>, <0>, <0>;
|
||||
|
||||
resets = <&clock_gcc GCC_PCIE_1_BCR>,
|
||||
<&clock_gcc GCC_PCIE_1_PHY_BCR>;
|
||||
|
|
@ -246,7 +311,73 @@
|
|||
qcom,phy-status-offset = <0x214>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x240>;
|
||||
qcom,phy-sequence = <0 0 0>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x0010 0x00 0x0
|
||||
0x001c 0x31 0x0
|
||||
0x0020 0x01 0x0
|
||||
0x0024 0xde 0x0
|
||||
0x0028 0x07 0x0
|
||||
0x0030 0x4c 0x0
|
||||
0x0034 0x06 0x0
|
||||
0x0048 0x90 0x0
|
||||
0x0058 0x0f 0x0
|
||||
0x0074 0x06 0x0
|
||||
0x0078 0x06 0x0
|
||||
0x007c 0x16 0x0
|
||||
0x0080 0x16 0x0
|
||||
0x0084 0x36 0x0
|
||||
0x0088 0x36 0x0
|
||||
0x0094 0x08 0x0
|
||||
0x00a4 0x42 0x0
|
||||
0x00ac 0x0a 0x0
|
||||
0x00b0 0x1a 0x0
|
||||
0x00b4 0x14 0x0
|
||||
0x00b8 0x34 0x0
|
||||
0x00bc 0x82 0x0
|
||||
0x00c4 0x68 0x0
|
||||
0x00cc 0x55 0x0
|
||||
0x00d0 0x55 0x0
|
||||
0x00d4 0x03 0x0
|
||||
0x00d8 0xab 0x0
|
||||
0x00dc 0xaa 0x0
|
||||
0x00e0 0x02 0x0
|
||||
0x010c 0x02 0x0
|
||||
0x0110 0x24 0x0
|
||||
0x0118 0xb4 0x0
|
||||
0x011c 0x03 0x0
|
||||
0x0154 0x34 0x0
|
||||
0x0158 0x01 0x0
|
||||
0x016c 0x08 0x0
|
||||
0x01ac 0xb9 0x0
|
||||
0x01b0 0x1e 0x0
|
||||
0x01b4 0x94 0x0
|
||||
0x01b8 0x18 0x0
|
||||
0x01bc 0x11 0x0
|
||||
0x1400 0x02 0x0
|
||||
0x1404 0x01 0x0
|
||||
0x1408 0x01 0x0
|
||||
0x0ee4 0x02 0x0
|
||||
0x16e4 0x20 0x0
|
||||
0x115c 0xff 0x0
|
||||
0x1160 0xbf 0x0
|
||||
0x1164 0xbf 0x0
|
||||
0x1168 0x7f 0x0
|
||||
0x116c 0xc8 0x0
|
||||
0x195c 0xff 0x0
|
||||
0x1960 0xbf 0x0
|
||||
0x1964 0xbf 0x0
|
||||
0x1968 0x7f 0x0
|
||||
0x196c 0xc8 0x0
|
||||
0x02dc 0x05 0x0
|
||||
0x0388 0x88 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x03e0 0x0f 0x0
|
||||
0x060c 0x1d 0x0
|
||||
0x0614 0x07 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue