Merge "ARM: dts: msm: Add hw gcc reset for sdcc on holi"

This commit is contained in:
qctecmdr 2020-10-15 05:37:56 -07:00 • committed by Gerrit - the friendly Code Review server
commit 33a9c60af0

View file

@ -2182,6 +2182,8 @@
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
@ -2189,6 +2191,10 @@
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {