Merge tag 'LA.UM.9.14.r1-22200-LAHAINA.QSSI14.0' of https://git.codelinaro.org/clo/la/kernel/msm-5.4 into android13-5.4-lahaina

"LA.UM.9.14.r1-22200-LAHAINA.QSSI14.0"

* tag 'LA.UM.9.14.r1-22200-LAHAINA.QSSI14.0' of https://git.codelinaro.org/clo/la/kernel/msm-5.4:
  usb: gadget: cdev: Add spinlock to synchronize ports->cbits_updated
  msm: ep_pcie: Set clock power management bit for EP
  msm: Add config option for R8168 IOSS glue driver
  ipa_eth: Header change to pass more info from ETH to GSI

Change-Id: Ib6b27009e9867a605881464b80926daf6e0da25b
This commit is contained in:
Michael Bestas 2023-08-25 12:11:25 +03:00
commit 36c61ad7d9
No known key found for this signature in database
GPG key ID: CC95044519BE6669
4 changed files with 24 additions and 1 deletions

View file

@ -190,6 +190,18 @@ config R8125_IOSS
To compile this driver as a module, choose M here. Module will be
called r8125_ioss. If unsure, say N.
config R8168_IOSS
tristate "Realtek R8168 IOSS glue driver"
depends on R8168
depends on IOSS
help
Enables IPA Ethernet Offload path on Realtek R8168 NIC. It is
designed to support generic HW processing of UL/DL IP packets for
various use cases to reduce the CPU load during E2E IP traffic.
To compile this driver as a module, choose M here. Module will be
called r8168_ioss. If unsure, say N.
config AQFWD_IOSS
tristate "AQC glue driver for IOSS v2"
depends on AQFWD

View file

@ -828,6 +828,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
ep_pcie_write_mask(dev->dm_core + PCIE20_L1SUB_CAPABILITY, 0,
0x1f);
/* Set CLK_PM_EN which allows to configure the clock-power-man bit below for EP */
ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 1, BIT(7));
/* Enable Clock Power Management */
ep_pcie_write_reg_field(dev->dm_core, PCIE20_LINK_CAPABILITIES,
PCIE20_MASK_CLOCK_POWER_MAN, 0x1);

View file

@ -1617,6 +1617,7 @@ static long f_cdev_ioctl(struct file *fp, unsigned int cmd,
int i = 0;
uint32_t val;
struct f_cdev *port;
unsigned long flags;
port = fp->private_data;
if (!port) {
@ -1638,11 +1639,13 @@ static long f_cdev_ioctl(struct file *fp, unsigned int cmd,
break;
case TIOCMGET:
pr_debug("TIOCMGET on port(%s)%pK\n", port->name, port);
spin_lock_irqsave(&port->port_lock, flags);
ret = f_cdev_tiocmget(port);
if (ret >= 0) {
ret = put_user(ret, (uint32_t *)arg);
port->cbits_updated = false;
}
spin_unlock_irqrestore(&port->port_lock, flags);
break;
default:
pr_err("Received cmd:%d not supported\n", cmd);
@ -1658,6 +1661,7 @@ static void usb_cser_notify_modem(void *fport, int ctrl_bits)
int temp;
struct f_cdev *port = fport;
struct cserial *cser;
unsigned long flags;
cser = &port->port_usb;
if (!port) {
@ -1672,6 +1676,7 @@ static void usb_cser_notify_modem(void *fport, int ctrl_bits)
if (temp == port->cbits_to_modem)
return;
spin_lock_irqsave(&port->port_lock, flags);
port->cbits_to_modem = temp;
port->cbits_updated = true;
@ -1686,6 +1691,7 @@ static void usb_cser_notify_modem(void *fport, int ctrl_bits)
cser->send_modem_ctrl_bits(cser, cbits_to_laptop);
}
spin_unlock_irqrestore(&port->port_lock, flags);
wake_up(&port->read_wq);
}

View file

@ -2,7 +2,7 @@
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _IPA_ETH_H_
@ -109,12 +109,14 @@ struct ipa_eth_aqc_setup_info {
* @bar_size: bar region size
* @queue_number: Which RTK queue to check the status on
* @dest_tail_ptr_offs: tail ptr offset
* @num_queues_enabled: Total queues to be enable
*/
struct ipa_eth_realtek_setup_info {
phys_addr_t bar_addr;
u32 bar_size;
u8 queue_number;
phys_addr_t dest_tail_ptr_offs;
u8 num_queues_enabled;
};