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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
Merge "msm: kgsl: Add a6xx GMU performance counters"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
37538bd8f3
16 changed files with 382 additions and 84 deletions
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@ -983,6 +983,36 @@
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x1F84D
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x1F84E
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x1F84F
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L 0x1F850
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H 0x1F851
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L 0x1F852
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H 0x1F853
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2 0x1F860
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L 0x1F870
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H 0x1F871
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L 0x1F872
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H 0x1F843
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L 0x1F874
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H 0x1F875
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L 0x1F876
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H 0x1F877
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#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L 0x1F888
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#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H 0x1F889
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE 0x1F8A0
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0 0x1F8A1
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1 0x1F8A2
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_L 0x1F8A4
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_H 0x1F8A5
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_L 0x1F8A6
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_H 0x1F8A7
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_L 0x1F8A8
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_H 0x1F8A9
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_L 0x1F8AA
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_H 0x1F8AB
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_L 0x1F8AC
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_H 0x1F8AD
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_L 0x1F8AE
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_H 0x1F8AF
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x1F8C0
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#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x1F8C1
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#define A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x1F8C2
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@ -26,6 +26,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
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DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),
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.features = ADRENO_SOFT_FAULT_DETECT,
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.gpudev = &adreno_a3xx_gpudev,
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.perfcounters = &adreno_a3xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_128K,
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.bus_width = 0,
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@ -48,6 +49,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
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DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),
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.features = ADRENO_SOFT_FAULT_DETECT,
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.gpudev = &adreno_a3xx_gpudev,
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.perfcounters = &adreno_a3xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_128K,
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.bus_width = 16,
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@ -68,6 +70,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
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DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),
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.features = ADRENO_SOFT_FAULT_DETECT,
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.gpudev = &adreno_a3xx_gpudev,
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.perfcounters = &adreno_a3xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = (SZ_64K + SZ_32K),
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.bus_width = 0,
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@ -192,6 +195,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
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ADRENO_PREEMPTION |
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ADRENO_CONTENT_PROTECTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M,
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.bus_width = 32,
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@ -218,6 +222,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
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ADRENO_PREEMPTION |
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ADRENO_CONTENT_PROTECTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M,
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.bus_width = 32,
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@ -284,6 +289,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
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DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
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.features = ADRENO_PREEMPTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_8K),
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.bus_width = 16,
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@ -303,6 +309,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
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.features = ADRENO_PREEMPTION |
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ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_8K),
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.bus_width = 16,
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@ -381,6 +388,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
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.base = {
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DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_256K,
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.bus_width = 16,
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@ -506,6 +514,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
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ADRENO_CONTENT_PROTECTION |
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ADRENO_GPMU | ADRENO_SPTP_PC,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M,
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.bus_width = 32,
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@ -589,6 +598,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
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.features = ADRENO_PREEMPTION |
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ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_256K + SZ_16K),
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.bus_width = 32,
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@ -608,6 +618,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
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.features = ADRENO_PREEMPTION |
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ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
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.gpudev = &adreno_a5xx_gpudev,
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.perfcounters = &adreno_a5xx_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_8K),
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.bus_width = 32,
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@ -783,6 +794,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |
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ADRENO_IOCOHERENT | ADRENO_PREEMPTION,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a630_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M,
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.bus_width = 32,
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@ -882,6 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -909,6 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -936,6 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -962,6 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = {
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.compatible = "qcom,adreno-gpu-a619-holi",
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.features = ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,
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.gpudev = &adreno_a619_holi_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -1076,7 +1092,12 @@ static const struct a6xx_protected_regs a620_protected_regs[] = {
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{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },
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{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },
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{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },
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{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },
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{ A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 },
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{ A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 },
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{ A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 },
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{ A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 },
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{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
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{ 0 },
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};
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@ -1088,6 +1109,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
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ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
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ADRENO_APRIV,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -1178,6 +1200,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
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ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
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ADRENO_IFPC | ADRENO_PREEMPTION,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M, //Verified 1MB
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.bus_width = 32,
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@ -1258,6 +1281,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
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ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
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ADRENO_IFPC | ADRENO_APRIV,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
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.bus_width = 32,
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@ -1287,6 +1311,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
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ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
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ADRENO_LM | ADRENO_APRIV,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
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.bus_width = 32,
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@ -1313,6 +1338,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
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DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),
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.features = ADRENO_RPMH | ADRENO_GPMU,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_2M,
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.bus_width = 32,
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@ -1390,6 +1416,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
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ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |
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ADRENO_IFPC,
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.gpudev = &adreno_a6xx_rgmu_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_4K),
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.bus_width = 32,
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@ -1415,6 +1442,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -1441,6 +1469,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
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.features = ADRENO_CONTENT_PROTECTION |
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ADRENO_PREEMPTION,
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.gpudev = &adreno_a6xx_gpudev,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_4K),
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.bus_width = 32,
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@ -1545,7 +1574,13 @@ static const struct a6xx_protected_regs a660_protected_regs[] = {
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{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },
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{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },
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{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },
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{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },
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{ A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 },
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{ A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 },
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{ A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 },
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{ A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 },
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{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
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{ 0 },
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};
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@ -1556,6 +1591,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
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ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
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ADRENO_IFPC | ADRENO_PREEMPTION,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_1M + SZ_512K,
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.bus_width = 32,
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@ -1588,6 +1624,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = {
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ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
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ADRENO_BCL,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.gmem_base = 0,
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.gmem_size = SZ_1M + SZ_512K,
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.bus_width = 32,
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|
|
@ -1620,6 +1657,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = {
|
|||
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
|
||||
ADRENO_IFPC | ADRENO_PREEMPTION,
|
||||
.gpudev = &adreno_a6xx_gmu_gpudev,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.gmem_base = 0,
|
||||
.gmem_size = SZ_1M + SZ_512K,
|
||||
.bus_width = 32,
|
||||
|
|
|
|||
|
|
@ -392,6 +392,7 @@ struct adreno_gpu_core {
|
|||
const char *compatible;
|
||||
unsigned long features;
|
||||
struct adreno_gpudev *gpudev;
|
||||
const struct adreno_perfcounters *perfcounters;
|
||||
unsigned long gmem_base;
|
||||
size_t gmem_size;
|
||||
u32 bus_width;
|
||||
|
|
@ -762,8 +763,6 @@ struct adreno_gpudev {
|
|||
const struct adreno_ft_perf_counters *ft_perf_counters;
|
||||
unsigned int ft_perf_counters_count;
|
||||
|
||||
struct adreno_perfcounters *perfcounters;
|
||||
|
||||
struct adreno_coresight *coresight[2];
|
||||
|
||||
unsigned int vbif_xin_halt_ctrl0_mask;
|
||||
|
|
|
|||
|
|
@ -1236,7 +1236,6 @@ struct adreno_gpudev adreno_a3xx_gpudev = {
|
|||
.reg_offsets = a3xx_register_offsets,
|
||||
.ft_perf_counters = a3xx_ft_perf_counters,
|
||||
.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),
|
||||
.perfcounters = &adreno_a3xx_perfcounters,
|
||||
.irq_handler = a3xx_irq_handler,
|
||||
.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,
|
||||
.probe = a3xx_probe,
|
||||
|
|
|
|||
|
|
@ -44,6 +44,6 @@ unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev);
|
|||
void a3xx_snapshot(struct adreno_device *adreno_dev,
|
||||
struct kgsl_snapshot *snapshot);
|
||||
|
||||
extern struct adreno_perfcounters adreno_a3xx_perfcounters;
|
||||
extern const struct adreno_perfcounters adreno_a3xx_perfcounters;
|
||||
|
||||
#endif /*__A3XX_H */
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
|
||||
|
||||
static int a3xx_counter_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -32,7 +32,7 @@ static int a3xx_counter_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static u64 a3xx_counter_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -52,14 +52,14 @@ static u64 a3xx_counter_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a3xx_counter_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -83,7 +83,7 @@ static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -113,7 +113,7 @@ static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -133,7 +133,7 @@ static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -154,7 +154,7 @@ static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static u64 a3xx_counter_vbif_pwr_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -356,7 +356,8 @@ static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = {
|
|||
#define A3XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read) \
|
||||
ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, offset, name, flags, enable, read)
|
||||
|
||||
static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
|
||||
static const struct adreno_perfcount_group
|
||||
a3xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A3XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a3xx_counter_enable, a3xx_counter_read),
|
||||
A3XX_PERFCOUNTER_GROUP(RBBM, rbbm,
|
||||
|
|
@ -392,7 +393,7 @@ static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
|
|||
|
||||
};
|
||||
|
||||
struct adreno_perfcounters adreno_a3xx_perfcounters = {
|
||||
const struct adreno_perfcounters adreno_a3xx_perfcounters = {
|
||||
a3xx_perfcounter_groups,
|
||||
ARRAY_SIZE(a3xx_perfcounter_groups),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2648,7 +2648,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
|
|||
.irq_handler = a5xx_irq_handler,
|
||||
.rb_start = a5xx_rb_start,
|
||||
.microcode_read = a5xx_microcode_read,
|
||||
.perfcounters = &adreno_a5xx_perfcounters,
|
||||
.vbif_xin_halt_ctrl0_mask = A5XX_VBIF_XIN_HALT_CTRL0_MASK,
|
||||
.is_sptp_idle = a5xx_is_sptp_idle,
|
||||
.regulator_enable = a5xx_regulator_enable,
|
||||
|
|
|
|||
|
|
@ -239,6 +239,6 @@ void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit);
|
|||
|
||||
u64 a5xx_read_alwayson(struct adreno_device *adreno_dev);
|
||||
|
||||
extern struct adreno_perfcounters adreno_a5xx_perfcounters;
|
||||
extern const struct adreno_perfcounters adreno_a5xx_perfcounters;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
|
||||
|
||||
static u64 a5xx_counter_read_norestore(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -31,7 +31,7 @@ static u64 a5xx_counter_read_norestore(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -44,7 +44,7 @@ static int a5xx_counter_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_rbbm_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
if (adreno_is_a540(adreno_dev) && countable == A5XX_RBBM_ALWAYS_COUNT)
|
||||
|
|
@ -54,7 +54,7 @@ static int a5xx_counter_rbbm_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static u64 a5xx_counter_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -68,7 +68,7 @@ static u64 a5xx_counter_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_vbif_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -98,7 +98,7 @@ static int a5xx_counter_vbif_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -120,14 +120,14 @@ static int a5xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_alwayson_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 a5xx_counter_alwayson_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct adreno_perfcount_register *reg = &group->regs[counter];
|
||||
|
|
@ -136,7 +136,7 @@ static u64 a5xx_counter_alwayson_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -150,7 +150,7 @@ static int a5xx_counter_pwr_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_pwr_gpmu_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -173,7 +173,7 @@ static int a5xx_counter_pwr_gpmu_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a5xx_counter_pwr_alwayson_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -621,7 +621,7 @@ static struct adreno_perfcount_group a5xx_perfcounter_groups
|
|||
a5xx_counter_pwr_alwayson_enable, a5xx_counter_read_norestore),
|
||||
};
|
||||
|
||||
struct adreno_perfcounters adreno_a5xx_perfcounters = {
|
||||
const struct adreno_perfcounters adreno_a5xx_perfcounters = {
|
||||
a5xx_perfcounter_groups,
|
||||
ARRAY_SIZE(a5xx_perfcounter_groups),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2422,7 +2422,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
|
|||
.rb_start = a6xx_rb_start,
|
||||
.regulator_enable = a6xx_sptprac_enable,
|
||||
.regulator_disable = a6xx_sptprac_disable,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.microcode_read = a6xx_microcode_read,
|
||||
.gpu_keepalive = a6xx_gpu_keepalive,
|
||||
|
|
@ -2452,7 +2451,6 @@ struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
|
|||
.probe = a6xx_hwsched_probe,
|
||||
.snapshot = a6xx_hwsched_snapshot,
|
||||
.irq_handler = a6xx_irq_handler,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.iommu_fault_block = a6xx_iommu_fault_block,
|
||||
.preemption_context_init = a6xx_preemption_context_init,
|
||||
|
|
@ -2474,7 +2472,6 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
|
|||
.rb_start = a6xx_rb_start,
|
||||
.regulator_enable = a6xx_sptprac_enable,
|
||||
.regulator_disable = a6xx_sptprac_disable,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.microcode_read = a6xx_microcode_read,
|
||||
.gpu_keepalive = a6xx_gpu_keepalive,
|
||||
|
|
@ -2506,7 +2503,6 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
|
|||
.rb_start = a6xx_rb_start,
|
||||
.regulator_enable = a6xx_sptprac_enable,
|
||||
.regulator_disable = a6xx_sptprac_disable,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.microcode_read = a6xx_microcode_read,
|
||||
.gpu_keepalive = a6xx_gpu_keepalive,
|
||||
|
|
@ -2538,7 +2534,6 @@ struct adreno_gpudev adreno_a619_holi_gpudev = {
|
|||
.rb_start = a6xx_rb_start,
|
||||
.regulator_enable = a6xx_sptprac_enable,
|
||||
.regulator_disable = a6xx_sptprac_disable,
|
||||
.perfcounters = &adreno_a6xx_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.microcode_read = a6xx_microcode_read,
|
||||
.gpu_keepalive = a6xx_gpu_keepalive,
|
||||
|
|
@ -2573,7 +2568,6 @@ struct adreno_gpudev adreno_a630_gpudev = {
|
|||
.rb_start = a6xx_rb_start,
|
||||
.regulator_enable = a6xx_sptprac_enable,
|
||||
.regulator_disable = a6xx_sptprac_disable,
|
||||
.perfcounters = &adreno_a630_perfcounters,
|
||||
.read_throttling_counters = a6xx_read_throttling_counters,
|
||||
.microcode_read = a6xx_microcode_read,
|
||||
.gpu_keepalive = a6xx_gpu_keepalive,
|
||||
|
|
|
|||
|
|
@ -419,6 +419,7 @@ void a6xx_spin_idle_debug(struct adreno_device *adreno_dev,
|
|||
int a6xx_perfcounter_update(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_register *reg, bool update_reg);
|
||||
|
||||
extern struct adreno_perfcounters adreno_a630_perfcounters;
|
||||
extern struct adreno_perfcounters adreno_a6xx_perfcounters;
|
||||
extern const struct adreno_perfcounters adreno_a630_perfcounters;
|
||||
extern const struct adreno_perfcounters adreno_a6xx_perfcounters;
|
||||
extern const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
* the stored shadow value
|
||||
*/
|
||||
static u64 a6xx_counter_read_norestore(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -48,7 +48,7 @@ static u64 a6xx_counter_read_norestore(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a6xx_counter_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -67,7 +67,7 @@ static int a6xx_counter_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a6xx_counter_inline_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -130,7 +130,7 @@ static int a6xx_counter_inline_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static u64 a6xx_counter_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -145,7 +145,7 @@ static u64 a6xx_counter_read(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a6xx_counter_gbif_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -176,7 +176,7 @@ static int a6xx_counter_gbif_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a630_counter_vbif_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -206,7 +206,7 @@ static int a630_counter_vbif_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a630_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -227,7 +227,7 @@ static int a630_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a6xx_counter_gbif_pwr_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
|
@ -254,14 +254,14 @@ static int a6xx_counter_gbif_pwr_enable(struct adreno_device *adreno_dev,
|
|||
}
|
||||
|
||||
static int a6xx_counter_alwayson_enable(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 a6xx_counter_alwayson_read(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter)
|
||||
{
|
||||
struct adreno_perfcount_register *reg = &group->regs[counter];
|
||||
|
|
@ -269,6 +269,99 @@ static u64 a6xx_counter_alwayson_read(struct adreno_device *adreno_dev,
|
|||
return a6xx_read_alwayson(adreno_dev) + reg->value;
|
||||
}
|
||||
|
||||
static void a6xx_write_gmu_counter_enable(struct kgsl_device *device,
|
||||
struct adreno_perfcount_register *reg, u32 bit, u32 countable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
kgsl_regread(device, reg->select, &val);
|
||||
val &= ~(0xff << bit);
|
||||
val |= countable << bit;
|
||||
kgsl_regwrite(device, reg->select, val);
|
||||
|
||||
}
|
||||
|
||||
static int a6xx_counter_gmu_xoclk_enable(struct adreno_device *adreno_dev,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct adreno_perfcount_register *reg = &group->regs[counter];
|
||||
|
||||
if (countable > 0xff)
|
||||
return -EINVAL;
|
||||
|
||||
if (counter >= 6 && !adreno_is_a660(adreno_dev))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24
|
||||
* Counters [4:5] are in select 2 bit offset 0, 8
|
||||
* Counters [6:9] are in select 3 bit offset 0, 8, 16 and 24
|
||||
*/
|
||||
|
||||
if (counter == 4 || counter == 5)
|
||||
counter -= 4;
|
||||
else if (counter >= 6)
|
||||
counter -= 6;
|
||||
|
||||
a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);
|
||||
|
||||
reg->value = 0;
|
||||
|
||||
kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int a6xx_counter_gmu_gmuclk_enable(struct adreno_device *adreno_dev,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct adreno_perfcount_register *reg = &group->regs[counter];
|
||||
|
||||
if (countable > 0xff)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* The two counters are stuck into GMU_CX_GMU_POWER_COUNTER_SELECT_1
|
||||
* at bit offset 16 and 24
|
||||
*/
|
||||
a6xx_write_gmu_counter_enable(device, reg,
|
||||
16 + (counter * 8), countable);
|
||||
|
||||
kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
|
||||
|
||||
reg->value = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int a6xx_counter_gmu_perf_enable(struct adreno_device *adreno_dev,
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct adreno_perfcount_register *reg = &group->regs[counter];
|
||||
|
||||
if (countable > 0xff)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24
|
||||
* Counters [4:5] are in select 2 bit offset 0, 8
|
||||
*/
|
||||
|
||||
if (counter >= 4)
|
||||
counter -= 4;
|
||||
|
||||
a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);
|
||||
|
||||
kgsl_regwrite(device, A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE, 1);
|
||||
|
||||
reg->value = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_0_LO,
|
||||
|
|
@ -611,6 +704,73 @@ static struct adreno_perfcount_register a6xx_perfcounters_gbif_pwr[] = {
|
|||
A6XX_GBIF_PWR_CNT_HIGH2, -1, A6XX_GBIF_PERF_PWR_CNT_EN },
|
||||
};
|
||||
|
||||
#define GMU_COUNTER(lo, hi, sel) \
|
||||
{ .countable = KGSL_PERFCOUNTER_NOT_USED, \
|
||||
.offset = lo, .offset_hi = hi, .select = sel }
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_gmu_xoclk[] = {
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_gmu_gmuclk[] = {
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_gmu_perf[] = {
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_0_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_0_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_1_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_1_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_2_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_2_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_3_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_3_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_4_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_4_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_5_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_5_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_CP_ALWAYS_ON_COUNTER_LO,
|
||||
A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },
|
||||
|
|
@ -630,7 +790,7 @@ static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {
|
|||
#define A6XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read) \
|
||||
ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, flags, enable, read)
|
||||
|
||||
static struct adreno_perfcount_group a630_perfcounter_groups
|
||||
static const struct adreno_perfcount_group a630_perfcounter_groups
|
||||
[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A6XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
|
|
@ -674,8 +834,8 @@ static struct adreno_perfcount_group a630_perfcounter_groups
|
|||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_group a6xx_perfcounter_groups
|
||||
[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
static const struct adreno_perfcount_group
|
||||
a6xx_legacy_perfcounter_groups [KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A6XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0,
|
||||
|
|
@ -718,12 +878,71 @@ static struct adreno_perfcount_group a6xx_perfcounter_groups
|
|||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
};
|
||||
|
||||
struct adreno_perfcounters adreno_a630_perfcounters = {
|
||||
static const struct adreno_perfcount_group a6xx_perfcounter_groups
|
||||
[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A6XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(PC, pc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VFD, vfd,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(HLSQ, hlsq,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VPC, vpc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(CCU, ccu,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(CMP, cmp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(TSE, tse,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(RAS, ras,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(LRZ, lrz,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(UCHE, uche,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(TP, tp,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(SP, sp,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(RB, rb,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VSC, vsc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF, gbif, 0,
|
||||
a6xx_counter_gbif_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, gbif_pwr,
|
||||
ADRENO_PERFCOUNTER_GROUP_FIXED,
|
||||
a6xx_counter_gbif_pwr_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,
|
||||
ADRENO_PERFCOUNTER_GROUP_FIXED,
|
||||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_XOCLK, gmu_xoclk, 0,
|
||||
a6xx_counter_gmu_xoclk_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_GMUCLK, gmu_gmuclk, 0,
|
||||
a6xx_counter_gmu_gmuclk_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_PERF, gmu_perf, 0,
|
||||
a6xx_counter_gmu_perf_enable, a6xx_counter_read_norestore),
|
||||
};
|
||||
|
||||
/* a610, a612, a616, a618 and a619 do not have the GMU registers.
|
||||
* a605, a608, a615, a630, a640 and a680 don't have enough room in the
|
||||
* CP_PROTECT registers so the GMU counters are not accessible
|
||||
*/
|
||||
const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters = {
|
||||
a6xx_legacy_perfcounter_groups,
|
||||
ARRAY_SIZE(a6xx_legacy_perfcounter_groups),
|
||||
};
|
||||
|
||||
const struct adreno_perfcounters adreno_a630_perfcounters = {
|
||||
a630_perfcounter_groups,
|
||||
ARRAY_SIZE(a630_perfcounter_groups),
|
||||
};
|
||||
|
||||
struct adreno_perfcounters adreno_a6xx_perfcounters = {
|
||||
const struct adreno_perfcounters adreno_a6xx_perfcounters = {
|
||||
a6xx_perfcounter_groups,
|
||||
ARRAY_SIZE(a6xx_perfcounter_groups),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,8 +67,9 @@ static void adreno_perfcounter_write(struct adreno_device *adreno_dev,
|
|||
*/
|
||||
void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int counter, groupid;
|
||||
|
||||
if (counters == NULL)
|
||||
|
|
@ -100,8 +101,9 @@ void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
|
|||
*/
|
||||
inline void adreno_perfcounter_save(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int counter, groupid;
|
||||
|
||||
if (counters == NULL)
|
||||
|
|
@ -142,8 +144,9 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
|
|||
|
||||
void adreno_perfcounter_start(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int i, j;
|
||||
|
||||
if (counters == NULL)
|
||||
|
|
@ -185,8 +188,9 @@ int adreno_perfcounter_read_group(struct adreno_device *adreno_dev,
|
|||
struct kgsl_perfcounter_read_group __user *reads, unsigned int count)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
struct kgsl_perfcounter_read_group *list = NULL;
|
||||
unsigned int i, j;
|
||||
int ret = 0;
|
||||
|
|
@ -266,8 +270,9 @@ done:
|
|||
int adreno_perfcounter_get_groupid(struct adreno_device *adreno_dev,
|
||||
const char *name)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
int i;
|
||||
|
||||
if (name == NULL || counters == NULL)
|
||||
|
|
@ -300,7 +305,8 @@ int adreno_perfcounter_get_groupid(struct adreno_device *adreno_dev,
|
|||
const char *adreno_perfcounter_get_name(struct adreno_device *adreno_dev,
|
||||
unsigned int groupid)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
|
||||
if (counters != NULL && groupid < counters->group_count)
|
||||
return counters->groups[groupid].name;
|
||||
|
|
@ -324,8 +330,9 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev,
|
|||
unsigned int count, unsigned int *max_counters)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int i, t;
|
||||
int ret = 0;
|
||||
unsigned int *buf;
|
||||
|
|
@ -370,7 +377,7 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline void refcount_group(struct adreno_perfcount_group *group,
|
||||
static inline void refcount_group(const struct adreno_perfcount_group *group,
|
||||
unsigned int reg, unsigned int flags,
|
||||
unsigned int *lo, unsigned int *hi)
|
||||
{
|
||||
|
|
@ -404,8 +411,9 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev,
|
|||
unsigned int groupid, unsigned int countable, unsigned int *offset,
|
||||
unsigned int *offset_hi, unsigned int flags)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int empty = -1;
|
||||
int ret = 0;
|
||||
|
||||
|
|
@ -511,8 +519,9 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev,
|
|||
int adreno_perfcounter_put(struct adreno_device *adreno_dev,
|
||||
unsigned int groupid, unsigned int countable, unsigned int flags)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
unsigned int i;
|
||||
|
||||
if (counters == NULL || groupid >= counters->group_count)
|
||||
|
|
@ -563,8 +572,9 @@ int adreno_perfcounter_put(struct adreno_device *adreno_dev,
|
|||
static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
|
||||
unsigned int groupid, unsigned int counter, unsigned int countable)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
|
||||
if (counters == NULL)
|
||||
return -EINVAL;
|
||||
|
|
@ -592,8 +602,9 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
|
|||
uint64_t adreno_perfcounter_read(struct adreno_device *adreno_dev,
|
||||
unsigned int groupid, unsigned int counter)
|
||||
{
|
||||
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
|
||||
/* Lets hope this doesn't fail. Now subfunctions don't need to check */
|
||||
if (counters == NULL)
|
||||
|
|
|
|||
|
|
@ -8,8 +8,7 @@
|
|||
struct adreno_device;
|
||||
|
||||
/* ADRENO_PERFCOUNTERS - Given an adreno device, return the perfcounters list */
|
||||
#define ADRENO_PERFCOUNTERS(_a) \
|
||||
(ADRENO_GPU_DEVICE(_a) ? ADRENO_GPU_DEVICE(_a)->perfcounters : NULL)
|
||||
#define ADRENO_PERFCOUNTERS(_a) ((_a)->gpucore->perfcounters)
|
||||
|
||||
#define PERFCOUNTER_FLAG_NONE 0x0
|
||||
#define PERFCOUNTER_FLAG_KERNEL 0x1
|
||||
|
|
@ -49,10 +48,11 @@ struct adreno_perfcount_group {
|
|||
const char *name;
|
||||
unsigned long flags;
|
||||
int (*enable)(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group, unsigned int counter,
|
||||
unsigned int countable);
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter, unsigned int countable);
|
||||
u64 (*read)(struct adreno_device *adreno_dev,
|
||||
struct adreno_perfcount_group *group, unsigned int counter);
|
||||
const struct adreno_perfcount_group *group,
|
||||
unsigned int counter);
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -78,7 +78,7 @@ struct adreno_perfcount_group {
|
|||
* @group_count: total groups for this device
|
||||
*/
|
||||
struct adreno_perfcounters {
|
||||
struct adreno_perfcount_group *groups;
|
||||
const struct adreno_perfcount_group *groups;
|
||||
unsigned int group_count;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -954,9 +954,9 @@ static int profile_groups_print(struct seq_file *s, void *unused)
|
|||
{
|
||||
struct kgsl_device *device = (struct kgsl_device *) s->private;
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
||||
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
|
||||
struct adreno_perfcounters *counters = gpudev->perfcounters;
|
||||
struct adreno_perfcount_group *group;
|
||||
const struct adreno_perfcounters *counters =
|
||||
ADRENO_PERFCOUNTERS(adreno_dev);
|
||||
const struct adreno_perfcount_group *group;
|
||||
int i, j, used;
|
||||
|
||||
mutex_lock(&device->mutex);
|
||||
|
|
|
|||
|
|
@ -464,7 +464,14 @@ struct kgsl_context_property_fault {
|
|||
#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21
|
||||
#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22
|
||||
#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23
|
||||
#define KGSL_PERFCOUNTER_GROUP_MAX 0x24
|
||||
#define KGSL_PERFCOUNTER_GROUP_GLC 0x24
|
||||
#define KGSL_PERFCOUNTER_GROUP_FCHE 0x25
|
||||
#define KGSL_PERFCOUNTER_GROUP_MHUB 0x26
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_XOCLK 0x27
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_GMUCLK 0x28
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_PERF 0x29
|
||||
#define KGSL_PERFCOUNTER_GROUP_SW 0x2a
|
||||
#define KGSL_PERFCOUNTER_GROUP_MAX 0x2b
|
||||
|
||||
#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF
|
||||
#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE
|
||||
|
|
|
|||
Loading…
Reference in a new issue