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msm: kgsl: Add a6xx GMU performance counters
Add three new groups to the a6xx performance counters for a620, a650, and a660 to expose the GMU_XOCLK, GMU_GMUCLK and GMU_PERF counters. Change-Id: Ic0dedbad07805bee4b6977e683e1161e4d500c1c Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse
parent
ba7d8b8807
commit
7e2a1b51cd
5 changed files with 280 additions and 12 deletions
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@ -983,6 +983,36 @@
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x1F84D
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x1F84E
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x1F84F
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L 0x1F850
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H 0x1F851
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L 0x1F852
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H 0x1F853
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2 0x1F860
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L 0x1F870
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H 0x1F871
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L 0x1F872
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H 0x1F843
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L 0x1F874
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H 0x1F875
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L 0x1F876
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#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H 0x1F877
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#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L 0x1F888
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#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H 0x1F889
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE 0x1F8A0
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0 0x1F8A1
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1 0x1F8A2
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_L 0x1F8A4
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_H 0x1F8A5
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_L 0x1F8A6
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_H 0x1F8A7
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_L 0x1F8A8
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_H 0x1F8A9
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_L 0x1F8AA
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_H 0x1F8AB
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_L 0x1F8AC
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_H 0x1F8AD
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_L 0x1F8AE
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#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_H 0x1F8AF
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x1F8C0
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#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x1F8C1
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#define A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x1F8C2
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@ -894,7 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -922,7 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -950,7 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -977,7 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = {
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.compatible = "qcom,adreno-gpu-a619-holi",
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.features = ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,
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.gpudev = &adreno_a619_holi_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -1092,7 +1092,12 @@ static const struct a6xx_protected_regs a620_protected_regs[] = {
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{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },
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{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },
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{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },
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{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },
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{ A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 },
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{ A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 },
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{ A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 },
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{ A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 },
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{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
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{ 0 },
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};
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@ -1195,7 +1200,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
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ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
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ADRENO_IFPC | ADRENO_PREEMPTION,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_1M, //Verified 1MB
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.bus_width = 32,
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@ -1333,7 +1338,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
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DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),
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.features = ADRENO_RPMH | ADRENO_GPMU,
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.gpudev = &adreno_a6xx_gmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_2M,
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.bus_width = 32,
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@ -1411,7 +1416,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
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ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |
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ADRENO_IFPC,
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.gpudev = &adreno_a6xx_rgmu_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_4K),
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.bus_width = 32,
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@ -1437,7 +1442,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
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ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
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ADRENO_IOCOHERENT,
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.gpudev = &adreno_a630_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = SZ_512K,
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.bus_width = 32,
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@ -1464,7 +1469,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
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.features = ADRENO_CONTENT_PROTECTION |
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ADRENO_PREEMPTION,
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.gpudev = &adreno_a6xx_gpudev,
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.perfcounters = &adreno_a6xx_perfcounters,
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.perfcounters = &adreno_a6xx_legacy_perfcounters,
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.gmem_base = 0x100000,
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.gmem_size = (SZ_128K + SZ_4K),
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.bus_width = 32,
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@ -1569,7 +1574,13 @@ static const struct a6xx_protected_regs a660_protected_regs[] = {
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{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },
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{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },
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{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },
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{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },
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{ A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 },
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{ A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 },
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{ A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 },
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{ A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 },
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{ A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 },
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{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
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{ 0 },
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};
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@ -407,4 +407,5 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev,
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extern const struct adreno_perfcounters adreno_a630_perfcounters;
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extern const struct adreno_perfcounters adreno_a6xx_perfcounters;
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extern const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters;
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#endif
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@ -269,6 +269,99 @@ static u64 a6xx_counter_alwayson_read(struct adreno_device *adreno_dev,
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return a6xx_read_alwayson(adreno_dev) + reg->value;
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}
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static void a6xx_write_gmu_counter_enable(struct kgsl_device *device,
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struct adreno_perfcount_register *reg, u32 bit, u32 countable)
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{
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u32 val;
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kgsl_regread(device, reg->select, &val);
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val &= ~(0xff << bit);
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val |= countable << bit;
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kgsl_regwrite(device, reg->select, val);
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}
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static int a6xx_counter_gmu_xoclk_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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if (countable > 0xff)
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return -EINVAL;
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if (counter >= 6 && !adreno_is_a660(adreno_dev))
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return -EINVAL;
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/*
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* Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24
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* Counters [4:5] are in select 2 bit offset 0, 8
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* Counters [6:9] are in select 3 bit offset 0, 8, 16 and 24
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*/
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if (counter == 4 || counter == 5)
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counter -= 4;
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else if (counter >= 6)
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counter -= 6;
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a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);
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reg->value = 0;
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kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
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return 0;
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}
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static int a6xx_counter_gmu_gmuclk_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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if (countable > 0xff)
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return -EINVAL;
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/*
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* The two counters are stuck into GMU_CX_GMU_POWER_COUNTER_SELECT_1
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* at bit offset 16 and 24
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*/
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a6xx_write_gmu_counter_enable(device, reg,
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16 + (counter * 8), countable);
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kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
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reg->value = 0;
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return 0;
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}
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static int a6xx_counter_gmu_perf_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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if (countable > 0xff)
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return -EINVAL;
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/*
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* Counters [0:3] are in select 1 bit offsets 0, 8, 16 and 24
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* Counters [4:5] are in select 2 bit offset 0, 8
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*/
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if (counter >= 4)
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counter -= 4;
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a6xx_write_gmu_counter_enable(device, reg, counter * 8, countable);
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kgsl_regwrite(device, A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE, 1);
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reg->value = 0;
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return 0;
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}
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static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_0_LO,
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@ -611,6 +704,73 @@ static struct adreno_perfcount_register a6xx_perfcounters_gbif_pwr[] = {
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A6XX_GBIF_PWR_CNT_HIGH2, -1, A6XX_GBIF_PERF_PWR_CNT_EN },
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};
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#define GMU_COUNTER(lo, hi, sel) \
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{ .countable = KGSL_PERFCOUNTER_NOT_USED, \
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.offset = lo, .offset_hi = hi, .select = sel }
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static struct adreno_perfcount_register a6xx_perfcounters_gmu_xoclk[] = {
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
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GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L,
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A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H,
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A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2),
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};
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static struct adreno_perfcount_register a6xx_perfcounters_gmu_gmuclk[] = {
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||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H,
|
||||
A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_gmu_perf[] = {
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_0_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_0_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_1_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_1_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_2_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_2_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_3_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_3_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_4_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_4_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),
|
||||
GMU_COUNTER(A6XX_GMU_CX_GMU_PERF_COUNTER_5_L,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_5_H,
|
||||
A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1),
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_CP_ALWAYS_ON_COUNTER_LO,
|
||||
A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },
|
||||
|
|
@ -674,8 +834,8 @@ static const struct adreno_perfcount_group a630_perfcounter_groups
|
|||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
};
|
||||
|
||||
static const struct adreno_perfcount_group a6xx_perfcounter_groups
|
||||
[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
static const struct adreno_perfcount_group
|
||||
a6xx_legacy_perfcounter_groups [KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A6XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0,
|
||||
|
|
@ -718,6 +878,65 @@ static const struct adreno_perfcount_group a6xx_perfcounter_groups
|
|||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
};
|
||||
|
||||
static const struct adreno_perfcount_group a6xx_perfcounter_groups
|
||||
[KGSL_PERFCOUNTER_GROUP_MAX] = {
|
||||
A6XX_PERFCOUNTER_GROUP(CP, cp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(PC, pc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VFD, vfd,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(HLSQ, hlsq,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VPC, vpc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(CCU, ccu,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(CMP, cmp,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(TSE, tse,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(RAS, ras,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(LRZ, lrz,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(UCHE, uche,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(TP, tp,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(SP, sp,
|
||||
a6xx_counter_inline_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(RB, rb,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP(VSC, vsc,
|
||||
a6xx_counter_enable, a6xx_counter_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF, gbif, 0,
|
||||
a6xx_counter_gbif_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, gbif_pwr,
|
||||
ADRENO_PERFCOUNTER_GROUP_FIXED,
|
||||
a6xx_counter_gbif_pwr_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,
|
||||
ADRENO_PERFCOUNTER_GROUP_FIXED,
|
||||
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_XOCLK, gmu_xoclk, 0,
|
||||
a6xx_counter_gmu_xoclk_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_GMUCLK, gmu_gmuclk, 0,
|
||||
a6xx_counter_gmu_gmuclk_enable, a6xx_counter_read_norestore),
|
||||
A6XX_PERFCOUNTER_GROUP_FLAGS(GMU_PERF, gmu_perf, 0,
|
||||
a6xx_counter_gmu_perf_enable, a6xx_counter_read_norestore),
|
||||
};
|
||||
|
||||
/* a610, a612, a616, a618 and a619 do not have the GMU registers.
|
||||
* a605, a608, a615, a630, a640 and a680 don't have enough room in the
|
||||
* CP_PROTECT registers so the GMU counters are not accessible
|
||||
*/
|
||||
const struct adreno_perfcounters adreno_a6xx_legacy_perfcounters = {
|
||||
a6xx_legacy_perfcounter_groups,
|
||||
ARRAY_SIZE(a6xx_legacy_perfcounter_groups),
|
||||
};
|
||||
|
||||
const struct adreno_perfcounters adreno_a630_perfcounters = {
|
||||
a630_perfcounter_groups,
|
||||
ARRAY_SIZE(a630_perfcounter_groups),
|
||||
|
|
|
|||
|
|
@ -464,7 +464,14 @@ struct kgsl_context_property_fault {
|
|||
#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21
|
||||
#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22
|
||||
#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23
|
||||
#define KGSL_PERFCOUNTER_GROUP_MAX 0x24
|
||||
#define KGSL_PERFCOUNTER_GROUP_GLC 0x24
|
||||
#define KGSL_PERFCOUNTER_GROUP_FCHE 0x25
|
||||
#define KGSL_PERFCOUNTER_GROUP_MHUB 0x26
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_XOCLK 0x27
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_GMUCLK 0x28
|
||||
#define KGSL_PERFCOUNTER_GROUP_GMU_PERF 0x29
|
||||
#define KGSL_PERFCOUNTER_GROUP_SW 0x2a
|
||||
#define KGSL_PERFCOUNTER_GROUP_MAX 0x2b
|
||||
|
||||
#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF
|
||||
#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE
|
||||
|
|
|
|||
Loading…
Reference in a new issue