A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-10 06:09:23 -04:00
Code Issues Projects Releases Packages Wiki Activity

clk: qcom: clk-rcg2: Fix QUPV3 DFSR M and N register mode overwrite

Browse source 
Move reading of MN counter mode register earlier to source sel
to fix overwrite of MN counter mode variable.

Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
This commit is contained in:
Vivek Aknurwar 2019-02-28 18:58:13 -08:00 • committed by David Collins
commit 3934ca8ec6
1 changed files with 4 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
drivers/clk/qcom/clk-rcg2.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -1243,6 +1243,9 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
if (cfg & mask)
f->pre_div = cfg & mask;
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
@ -1255,8 +1258,6 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
}
}
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
if (mode) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),