mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 00:24:41 -04:00
Merge "ARM: dts: msm: Add device node for llcc node on SM6150"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
3bfb7af600
2 changed files with 295 additions and 1 deletions
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@ -14,7 +14,7 @@ Properties:
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Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
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or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
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or "qcom,yupik-llcc" or "qcom,sm8150-llcc"
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or "qcom,sdmshrike-llcc"
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or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc"
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"qcom,llcc-v2" must be appended for V2 hardware.
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- reg:
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294
qcom/sm6150.dtsi
294
qcom/sm6150.dtsi
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@ -14,6 +14,12 @@
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
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opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
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opp-supported-hw = <ddrtype>;}
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/ {
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model = "Qualcomm Technologies, Inc. SM6150";
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compatible = "qcom,sm6150";
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@ -631,6 +637,262 @@
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};
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};
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llcc_pmu: llcc-pmu@90cc000 {
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compatible = "qcom,llcc-pmu-ver2";
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reg = <0x090cc000 0x300>;
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reg-names = "lagg-base";
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};
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llcc_bw_opp_table: llcc-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
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BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
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BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
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BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
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BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
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BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
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};
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cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
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compatible = "qcom,bimc-bwmon4";
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reg = <0x90b6300 0x300>, <0x90b6200 0x200>;
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reg-names = "base", "global_base";
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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qcom,mport = <0>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_cpu_llcc_bw>;
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qcom,count-unit = <0x10000>;
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};
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ddr_bw_opp_table: ddr-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
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BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
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BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
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BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
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BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
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BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
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BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
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BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
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BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
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BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
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};
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cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
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compatible = "qcom,bimc-bwmon5";
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reg = <0x90cd000 0x1000>;
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reg-names = "base";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_llcc_ddr_bw>;
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qcom,count-unit = <0x10000>;
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};
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cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18321110 0x500>;
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reg-names = "ftbl-base";
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qcom,ftbl-row-size = <0x20>;
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governor = "performance";
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interconnects = <&osm_l3 MASTER_OSM_L3_APPS
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&osm_l3 SLAVE_OSM_L3_CLUSTER0>;
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};
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cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
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qcom,core-dev-table =
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< 576000 300000000 >,
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< 1017600 556800000 >,
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< 1209660 806400000 >,
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< 1516800 940800000 >,
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< 1804800 1363200000 >;
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};
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cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
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compatible = "qcom,arm-memlat-cpugrp";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,target-dev = <&cpu0_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,stall-cycle-ev = <0xE7>;
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qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
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};
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cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,target-dev = <&cpu0_cpu_llcc_lat>;
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qcom,cachemiss-ev = <0x2A>;
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qcom,stall-cycle-ev = <0xE7>;
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qcom,core-dev-table =
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< 748000 MHZ_TO_MBPS(150, 16) >,
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< 1209600 MHZ_TO_MBPS(300, 16) >,
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< 1516800 MHZ_TO_MBPS(466, 16) >,
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< 1804800 MHZ_TO_MBPS(600, 16) >;
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};
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cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,target-dev = <&cpu0_llcc_ddr_lat>;
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qcom,cachemiss-ev = <0x1000>;
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qcom,core-dev-table =
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< 748000 MHZ_TO_MBPS( 300, 4) >,
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< 1017600 MHZ_TO_MBPS( 451, 4) >,
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< 1209600 MHZ_TO_MBPS( 547, 4) >,
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< 1516800 MHZ_TO_MBPS( 768, 4) >,
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< 1804800 MHZ_TO_MBPS(1017, 4) >;
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};
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cpu0_computemon: qcom,cpu0-computemon {
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compatible = "qcom,arm-compute-mon";
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qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
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qcom,core-dev-table =
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< 748800 MHZ_TO_MBPS( 300, 4) >,
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< 1209600 MHZ_TO_MBPS( 451, 4) >,
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< 1593600 MHZ_TO_MBPS( 547, 4) >,
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< 1804800 MHZ_TO_MBPS( 768, 4) >;
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};
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};
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cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18321110 0x500>;
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reg-names = "ftbl-base";
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qcom,ftbl-row-size = <0x20>;
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governor = "performance";
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interconnects = <&osm_l3 MASTER_OSM_L3_APPS
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&osm_l3 SLAVE_OSM_L3_CLUSTER1>;
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};
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cpu6_cpu_l3_tbl: qcom,cpu6_cpu_l3_tbl {
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qcom,core-dev-table =
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< 1017600 556800000 >,
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< 1209600 806400000 >,
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< 1516800 940800000 >,
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< 1708800 1209600000 >,
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< 2208000 1363200000 >;
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};
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cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu6_memlat_cpugrp: qcom,cpu6-cpugrp {
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compatible = "qcom,arm-memlat-cpugrp";
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qcom,cpulist = <&CPU6 &CPU7>;
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cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,target-dev = <&cpu6_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,stall-cycle-ev = <0x15E>;
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qcom,core-dev-table = <&cpu6_cpu_l3_tbl>;
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};
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cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,target-dev = <&cpu6_cpu_llcc_lat>;
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qcom,cachemiss-ev = <0x2A>;
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qcom,stall-cycle-ev = <0x15E>;
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qcom,core-dev-table =
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< 768000 MHZ_TO_MBPS(300, 16) >,
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< 1017600 MHZ_TO_MBPS(466, 16) >,
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< 1209600 MHZ_TO_MBPS(600, 16) >,
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< 1708800 MHZ_TO_MBPS(806, 16) >,
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< 2208000 MHZ_TO_MBPS(933, 16) >;
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};
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cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,target-dev = <&cpu6_llcc_ddr_lat>;
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qcom,cachemiss-ev = <0x1000>;
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qcom,core-dev-table =
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< 768000 MHZ_TO_MBPS( 451, 4) >,
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< 1017600 MHZ_TO_MBPS( 547, 4) >,
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< 1209600 MHZ_TO_MBPS(1017, 4) >,
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< 1708800 MHZ_TO_MBPS(1555, 4) >,
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< 2208000 MHZ_TO_MBPS(1804, 4) >;
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};
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cpu6_computemon: qcom,cpu6-computemon {
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compatible = "qcom,arm-compute-mon";
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qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
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qcom,core-dev-table =
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< 1017600 MHZ_TO_MBPS( 300, 4) >,
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< 1209600 MHZ_TO_MBPS( 547, 4) >,
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< 1516800 MHZ_TO_MBPS( 768, 4) >,
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< 1708800 MHZ_TO_MBPS(1017, 4) >,
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< 2208000 MHZ_TO_MBPS(1804, 4) >;
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm6150-pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
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@ -672,6 +934,19 @@
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};
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};
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cpu_pmu: cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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qcom,irq-is-percpu;
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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dsu_pmu@0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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qcom,msm-imem@146aa000 {
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compatible = "qcom,msm-imem";
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reg = <0x146aa000 0x1000>;
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@ -726,6 +1001,13 @@
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clock-frequency = <32768>;
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};
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cache-controller@9200000 {
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compatible = "qcom,sm6150-llcc";
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reg = <0x9200000 0x50000> , <0x9600000 0x50000>;
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reg-names = "llcc_base", "llcc_broadcast_base";
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cap-based-alloc-and-pwr-collapse;
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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@ -1845,6 +2127,18 @@
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vote = <67>;
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};
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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};
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#include "sm6150-qupv3.dtsi"
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Reference in a new issue