Merge "ARM: dts: msm: Add throttle clk support for shima"

This commit is contained in:
qctecmdr 2020-06-15 06:15:37 -07:00 • committed by Gerrit - the friendly Code Review server
commit 3c0d3b477f

View file

@ -15,15 +15,16 @@
vcodec-supply = <&video_cc_mvs0_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi0",
clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
qcom,proxy-clock-names = "gcc_video_axi0",
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
qcom,clock-configs = <0x0 0x1 0x1>;
qcom,clock-configs = <0x0 0x0 0x1 0x1>;
qcom,allowed-clock-rates = <240000000 338000000
364800000>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
@ -113,15 +114,16 @@
vcodec-supply = <&video_cc_mvs0_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi0",
clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
qcom,proxy-clock-names = "gcc_video_axi0",
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
qcom,clock-configs = <0x0 0x1 0x1>;
qcom,clock-configs = <0x0 0x0 0x1 0x1>;
qcom,allowed-clock-rates = <201600000>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
@ -210,15 +212,16 @@
vcodec-supply = <&video_cc_mvs0_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi0",
clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
qcom,proxy-clock-names = "gcc_video_axi0",
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle",
"core_clk", "vcodec_clk";
/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
qcom,clock-configs = <0x0 0x1 0x1>;
qcom,clock-configs = <0x0 0x0 0x1 0x1>;
qcom,allowed-clock-rates = <240000000 338000000
366000000 444000000>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,