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clk: qcom: remove flags for byte div clk src

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The change removes CLK_SET_RATE_PARENT flag for byte div clk
src dividers, as it would result in a set rate of byte clock
again after it has been set to the required rate.

Change-Id: Iff81adf9df2ad5457cc947190e5c10768fd5b270
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This commit is contained in:
Satya Rama Aditya Pinapala 2020-02-19 18:26:15 -08:00
commit 40bc88748d
1 changed files with 1 additions and 3 deletions
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4
drivers/clk/qcom/dispcc-lahaina.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
@ -805,7 +805,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
@ -820,7 +819,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};