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ARM: dts: msm: update max clk rate for display clocks

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Update max clk rates for mdp clks.

Change-Id: I1732f73d1646d8aa08ffbaebfd6afacda07baaaf
This commit is contained in:
Venkata Prahlad Valluru 2021-08-28 01:13:18 +05:30 • committed by chenyt17
commit 43ea792567
1 changed files with 2 additions and 2 deletions
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4
display/monaco-sde.dtsi
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@ -40,8 +40,8 @@
clock-names = "gcc_bus", "throttle_clk",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk";
clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;
clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;
clock-rate = <0 0 0 300000000 19200000 192000000>;
clock-max-rate = <0 0 0 400000000 19200000 400000000>;
sde-vdd-supply = <&mdss_core_gdsc>;