A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Add QDSS IPA bam connection config for sdxlemur

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Add QDSS IPA bam connection config for QDSS to pcie hw transfer.

Change-Id: Ia129b5f201a44b89d29ef91bb557616183af4c43
This commit is contained in:
Yuanfang Zhang 2020-12-09 18:54:48 +08:00
commit 47510aa48a
2 changed files with 10 additions and 0 deletions
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3
bindings/arm/coresight.txt
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@ -151,6 +151,9 @@ its hardware characteristcs.
* cti-flush-trig-num: Specifies the flush CTI trigger number for TMC
ETR and TMC ETF.
* qcom,qdss-ipa-support : indicates whether qdss to ipa bam connection
need to support.
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error for CATU and four interrupts for TGU to get trigger from four

7
qcom/sdxlemur-coresight.dtsi
View file

@ -148,6 +148,13 @@
arm,buffer-size = <0x400000>;
arm,scatter-gather;
qcom,qdss-ipa-support;
ipa-conn-data-base-pa = <0x1468B000>;
ipa-conn-data-size = <0x3000>;
ipa-conn-desc-base-pa = <0x1468E000>;
ipa-conn-desc-size = <0x1000>;
ipa-peer-evt-reg-pa = <0x6077818>;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti3_swao>;
cti-reset-trig-num = <0>;