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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 15:11:48 -04:00
Revert "ARM: dts: qcom: Enable the second UFS instance"
This reverts commit 7c4889dd68.
Change-Id: Ic5139ad1615332ac6d354a65e3fbcbbbec14635f
This commit is contained in:
Srinivas Ganji
Gerrit - the friendly Code Review server
parent
7c4889dd68
commit
47742e574a
3 changed files with 2 additions and 172 deletions
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@ -336,12 +336,10 @@
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L17A: pm8195_1_l17: regulator-pm8195-1-l17 {
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regulator-name = "pm8195_1_l17";
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qcom,set = <RPMH_REGULATOR_SET_ALL>;
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regulator-min-microvolt = <2504000>;
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3544000>;
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qcom,init-voltage = <2904000>;
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qcom,init-voltage = <1700000>;
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qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
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regulator-system-load = <1>;
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regulator-always-on;
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};
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};
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@ -696,7 +694,6 @@
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regulator-max-microvolt = <3544000>;
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qcom,init-voltage = <2500000>;
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qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
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regulator-always-on;
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};
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};
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@ -59,36 +59,6 @@
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status= "ok"
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};
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&ufs2phy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-phy-supply = <&pm8195_3_l5>;
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vdda-pll-supply = <&pm8195_1_l9>;
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vdda-phy-max-microamp = <138000>;
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vdda-pll-max-microamp = <65100>;
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status = "ok"
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};
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&ufshc2_mem {
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vdd-hba-supply = <&ufs_card_2_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8195_1_l17>;
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vcc-voltage-level = <2894000 2904000>;
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vcc-low-voltage-sup;
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vccq-supply = <&pm8195_2_l5>;
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vccq2-supply = <&pm8195_s4>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm8195_1_s2>;
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qcom,vccq-parent-max-microamp = <210000>;
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status= "ok"
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};
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&usb2_phy0 {
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vdd-supply = <&pm8195_3_l5>;
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vdda18-supply = <&pm8195_1_l12>;
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@ -35,7 +35,6 @@
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */
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serial0 = &qupv3_se12_2uart;
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sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
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spi22 = &qupv3_se22_spi;
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@ -1432,8 +1431,6 @@
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy_mem>;
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phy-names = "ufsphy";
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spm-level = <5>;
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rpm-level = <1>;
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#reset-cells = <1>;
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lanes-per-direction = <2>;
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@ -1539,140 +1536,6 @@
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status = "disabled";
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};
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ufs2phy_mem: ufsphy_mem@1d67000 {
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reg = <0x1d67000 0xe00>; /* PHY regs */
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reg-names = "phy_mem";
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#phy-cells = <0>;
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lanes-per-direction = <2>;
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clock-names = "ref_clk_src",
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"ref_clk",
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"ref_aux_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_CARD_CLKREF_CLK>,
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<&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>;
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resets = <&ufshc2_mem 0>;
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status = "disabled";
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};
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ufshc2_mem: ufshc@1d64000 {
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compatible = "qcom,ufshc";
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reg = <0x1d64000 0x3000>,
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<0x1d70000 0x8000>;
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reg-names = "ufs_mem", "ufs_ice";
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interrupts = <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs2phy_mem>;
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phy-names = "ufsphy";
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spm-level = <5>;
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rpm-level = <1>;
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#reset-cells = <1>;
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lanes-per-direction = <2>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_CARD_2_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,
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<&gcc GCC_UFS_CARD_2_AHB_CLK>,
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<&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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interconnects =
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<&aggre1_noc MASTER_UFS_GEN4 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_UFS_MEM_1_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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qcom,ufs-bus-bw,name = "ufshc_mem";
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qcom,ufs-bus-bw,num-cases = <26>;
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qcom,ufs-bus-bw,num-paths = <2>;
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qcom,ufs-bus-bw,vectors-KBps =
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/*
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* During HS G3 UFS runs at nominal voltage corner, vote
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* higher bandwidth to push other buses in the data path
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* to run at nominal to achieve max throughput.
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* 4GBps pushes BIMC to run at nominal.
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* 200MBps pushes CNOC to run at nominal.
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* Vote for half of this bandwidth for HS G3 1-lane.
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* For max bandwidth, vote high enough to push the buses
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* to run in turbo voltage corner.
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*/
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<0 0>, <0 0>, /* No vote */
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<922 0>, <1000 0>, /* PWM G1 */
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<1844 0>, <1000 0>, /* PWM G2 */
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<3688 0>, <1000 0>, /* PWM G3 */
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<7376 0>, <1000 0>, /* PWM G4 */
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<1844 0>, <1000 0>, /* PWM G1 L2 */
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<3688 0>, <1000 0>, /* PWM G2 L2 */
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<7376 0>, <1000 0>, /* PWM G3 L2 */
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<14752 0>, <1000 0>, /* PWM G4 L2 */
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<127796 0>, <1000 0>, /* HS G1 RA */
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<255591 0>, <1000 0>, /* HS G2 RA */
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<2097152 0>, <102400 0>, /* HS G3 RA */
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<4194304 0>, <204800 0>, /* HS G4 RA */
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<255591 0>, <1000 0>, /* HS G1 RA L2 */
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<511181 0>, <1000 0>, /* HS G2 RA L2 */
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<4194304 0>, <204800 0>, /* HS G3 RA L2 */
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<8388608 0>, <409600 0>, /* HS G4 RA L2 */
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<149422 0>, <1000 0>, /* HS G1 RB */
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<298189 0>, <1000 0>, /* HS G2 RB */
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<2097152 0>, <102400 0>, /* HS G3 RB */
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<4194304 0>, <204800 0>, /* HS G4 RB */
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<298189 0>, <1000 0>, /* HS G1 RB L2 */
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<596378 0>, <1000 0>, /* HS G2 RB L2 */
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/* As UFS working in HS G3 RB L2 mode, aggregated
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* bandwidth (AB) should take care of providing
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* optimum throughput requested. However, as tested,
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* in order to scale up CNOC clock, instantaneous
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* bindwidth (IB) needs to be given a proper value too.
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*/
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<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
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<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
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<7643136 0>, <307200 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
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"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
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"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
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"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
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"MAX";
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reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_UFS_CARD_2_BCR>;
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reset-names = "rst";
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secondary-storage;
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status = "disabled";
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};
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spmi_bus: qcom,spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0xc440000 0x1000>,
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