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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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qcacmn: Enable Shadow register from PCIe block in QCN7605
QCN7605 has 2 set of shadow registers, WCSS block and PCIe block. As PCIe shadow register are at power domain boundary, enabling PCIe shadow register for QCN7605. Also PCIe shadow register falls below 512KB, no need to use register windowing which is required to get it access from IPA FW Change-Id: If18d2d0a3f16f492b3c32449695e70c2b9942375 CRs-Fixed: 2623853
This commit is contained in:
Nirav Shah
nshrivas
parent
459060642c
commit
47fdeadbd1
1 changed files with 107 additions and 1 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@ -2825,6 +2825,111 @@ struct ce_reg_def genoa_ce_targetdef = {
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MISSING_FOR_ADRASTEA,
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};
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#ifdef QCN7605_PCIE_SHADOW_REG_SUPPORT
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#define PCIE_SHADOW_REG_VALUE_0 0x2F024
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#define PCIE_SHADOW_REG_VALUE_1 0x2F028
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#define PCIE_SHADOW_REG_VALUE_2 0x2F02C
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#define PCIE_SHADOW_REG_VALUE_3 0x2F030
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#define PCIE_SHADOW_REG_VALUE_4 0x2F034
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#define PCIE_SHADOW_REG_VALUE_5 0x2F038
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#define PCIE_SHADOW_REG_VALUE_6 0x2F03C
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#define PCIE_SHADOW_REG_VALUE_7 0x2F040
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#define PCIE_SHADOW_REG_VALUE_8 0x2F044
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#define PCIE_SHADOW_REG_VALUE_9 0x2F048
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#define PCIE_SHADOW_REG_VALUE_10 0x2F04C
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#define PCIE_SHADOW_REG_VALUE_11 0x2F050
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#define PCIE_SHADOW_REG_VALUE_12 0x2F054
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#define PCIE_SHADOW_REG_VALUE_13 0x2F058
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#define PCIE_SHADOW_REG_VALUE_14 0x2F05C
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#define PCIE_SHADOW_REG_VALUE_15 0x2F060
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#define PCIE_SHADOW_REG_VALUE_16 0x2F064
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#define PCIE_SHADOW_REG_VALUE_17 0x2F068
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#define PCIE_SHADOW_REG_VALUE_18 0x2F06C
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#define PCIE_SHADOW_REG_VALUE_19 0x2F070
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#define PCIE_SHADOW_REG_VALUE_20 0x2F074
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#define PCIE_SHADOW_REG_VALUE_21 0x2F078
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#define PCIE_SHADOW_REG_VALUE_22 0x2F07C
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#define PCIE_SHADOW_REG_VALUE_23 0x2F080
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#define PCIE_SHADOW_REG_INTER_ADDR_0 0x21000
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#define PCIE_SHADOW_REG_INTER_ADDR_1 0x21004
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#define PCIE_SHADOW_REG_INTER_ADDR_2 0x21008
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#define PCIE_SHADOW_REG_INTER_ADDR_3 0x2100C
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#define PCIE_SHADOW_REG_INTER_ADDR_4 0x21010
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#define PCIE_SHADOW_REG_INTER_ADDR_5 0x21014
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#define PCIE_SHADOW_REG_INTER_ADDR_6 0x21018
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#define PCIE_SHADOW_REG_INTER_ADDR_7 0x2101C
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#define PCIE_SHADOW_REG_INTER_ADDR_8 0x21020
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#define PCIE_SHADOW_REG_INTER_ADDR_9 0x21024
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#define PCIE_SHADOW_REG_INTER_ADDR_10 0x21028
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#define PCIE_SHADOW_REG_INTER_ADDR_11 0x2102C
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#define PCIE_SHADOW_REG_INTER_ADDR_12 0x21030
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#define PCIE_SHADOW_REG_INTER_ADDR_13 0x21034
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#define PCIE_SHADOW_REG_INTER_ADDR_14 0x21038
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#define PCIE_SHADOW_REG_INTER_ADDR_15 0x2103C
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#define PCIE_SHADOW_REG_INTER_ADDR_16 0x21040
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#define PCIE_SHADOW_REG_INTER_ADDR_17 0x21044
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#define PCIE_SHADOW_REG_INTER_ADDR_18 0x21048
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#define PCIE_SHADOW_REG_INTER_ADDR_19 0x2104C
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#define PCIE_SHADOW_REG_INTER_ADDR_20 0x21050
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#define PCIE_SHADOW_REG_INTER_ADDR_21 0x21054
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#define PCIE_SHADOW_REG_INTER_ADDR_22 0x21058
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#define PCIE_SHADOW_REG_INTER_ADDR_23 0x2105C
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struct host_shadow_regs_s genoa_host_shadow_regs = {
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.d_A_LOCAL_SHADOW_REG_VALUE_0 = PCIE_SHADOW_REG_VALUE_0,
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.d_A_LOCAL_SHADOW_REG_VALUE_1 = PCIE_SHADOW_REG_VALUE_1,
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.d_A_LOCAL_SHADOW_REG_VALUE_2 = PCIE_SHADOW_REG_VALUE_2,
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.d_A_LOCAL_SHADOW_REG_VALUE_3 = PCIE_SHADOW_REG_VALUE_3,
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.d_A_LOCAL_SHADOW_REG_VALUE_4 = PCIE_SHADOW_REG_VALUE_4,
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.d_A_LOCAL_SHADOW_REG_VALUE_5 = PCIE_SHADOW_REG_VALUE_5,
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.d_A_LOCAL_SHADOW_REG_VALUE_6 = PCIE_SHADOW_REG_VALUE_6,
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.d_A_LOCAL_SHADOW_REG_VALUE_7 = PCIE_SHADOW_REG_VALUE_7,
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.d_A_LOCAL_SHADOW_REG_VALUE_8 = PCIE_SHADOW_REG_VALUE_8,
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.d_A_LOCAL_SHADOW_REG_VALUE_9 = PCIE_SHADOW_REG_VALUE_9,
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.d_A_LOCAL_SHADOW_REG_VALUE_10 = PCIE_SHADOW_REG_VALUE_10,
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.d_A_LOCAL_SHADOW_REG_VALUE_11 = PCIE_SHADOW_REG_VALUE_11,
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.d_A_LOCAL_SHADOW_REG_VALUE_12 = PCIE_SHADOW_REG_VALUE_12,
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.d_A_LOCAL_SHADOW_REG_VALUE_13 = PCIE_SHADOW_REG_VALUE_13,
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.d_A_LOCAL_SHADOW_REG_VALUE_14 = PCIE_SHADOW_REG_VALUE_14,
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.d_A_LOCAL_SHADOW_REG_VALUE_15 = PCIE_SHADOW_REG_VALUE_15,
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.d_A_LOCAL_SHADOW_REG_VALUE_16 = PCIE_SHADOW_REG_VALUE_16,
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.d_A_LOCAL_SHADOW_REG_VALUE_17 = PCIE_SHADOW_REG_VALUE_17,
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.d_A_LOCAL_SHADOW_REG_VALUE_18 = PCIE_SHADOW_REG_VALUE_18,
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.d_A_LOCAL_SHADOW_REG_VALUE_19 = PCIE_SHADOW_REG_VALUE_19,
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.d_A_LOCAL_SHADOW_REG_VALUE_20 = PCIE_SHADOW_REG_VALUE_20,
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.d_A_LOCAL_SHADOW_REG_VALUE_21 = PCIE_SHADOW_REG_VALUE_21,
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.d_A_LOCAL_SHADOW_REG_VALUE_22 = PCIE_SHADOW_REG_VALUE_22,
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.d_A_LOCAL_SHADOW_REG_VALUE_23 = PCIE_SHADOW_REG_VALUE_23,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_0 = PCIE_SHADOW_REG_INTER_ADDR_0,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_1 = PCIE_SHADOW_REG_INTER_ADDR_1,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_2 = PCIE_SHADOW_REG_INTER_ADDR_2,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_3 = PCIE_SHADOW_REG_INTER_ADDR_3,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_4 = PCIE_SHADOW_REG_INTER_ADDR_4,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_5 = PCIE_SHADOW_REG_INTER_ADDR_5,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_6 = PCIE_SHADOW_REG_INTER_ADDR_6,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_7 = PCIE_SHADOW_REG_INTER_ADDR_7,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_8 = PCIE_SHADOW_REG_INTER_ADDR_8,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_9 = PCIE_SHADOW_REG_INTER_ADDR_9,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_10 = PCIE_SHADOW_REG_INTER_ADDR_10,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_11 = PCIE_SHADOW_REG_INTER_ADDR_11,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_12 = PCIE_SHADOW_REG_INTER_ADDR_12,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_13 = PCIE_SHADOW_REG_INTER_ADDR_13,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_14 = PCIE_SHADOW_REG_INTER_ADDR_14,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_15 = PCIE_SHADOW_REG_INTER_ADDR_15,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_16 = PCIE_SHADOW_REG_INTER_ADDR_16,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_17 = PCIE_SHADOW_REG_INTER_ADDR_17,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_18 = PCIE_SHADOW_REG_INTER_ADDR_18,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_19 = PCIE_SHADOW_REG_INTER_ADDR_19,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_20 = PCIE_SHADOW_REG_INTER_ADDR_20,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_21 = PCIE_SHADOW_REG_INTER_ADDR_21,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_22 = PCIE_SHADOW_REG_INTER_ADDR_22,
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.d_A_LOCAL_SHADOW_REG_ADDRESS_23 = PCIE_SHADOW_REG_INTER_ADDR_23,
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};
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#else
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struct host_shadow_regs_s genoa_host_shadow_regs = {
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.d_A_LOCAL_SHADOW_REG_VALUE_0 =
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GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0,
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@ -2923,5 +3028,6 @@ struct host_shadow_regs_s genoa_host_shadow_regs = {
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.d_A_LOCAL_SHADOW_REG_ADDRESS_23 =
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GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
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};
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#endif
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#endif /* ADRASTEA_REG_DEF_H */
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