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ARM: dts: qcom: Add support to disable PCIe halt Wr and Rd

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This will add the provision to control the PCIe halt Wr and Rd.
By setting this DT flag, PCIe halt Wr and Rd can be disabled.

In Olympic CPE targets observed degradation in throughput due to 
PCIe latencies with PCIe halt write/read feature. 
Hence, disabling the PCIe halt feature in Olympic CPE targets.

Change-Id: Iee945984e24f2a99d9e0b1e2a0323255decc28ef
This commit is contained in:
Jyothi Kumar Seerapu 2022-07-25 16:03:51 +05:30 • committed by Gerrit - the friendly Code Review server
commit 4a6ae6e0d8
2 changed files with 7 additions and 0 deletions
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6
bindings/pci/pci-msm.txt
View file

@ -407,12 +407,18 @@ interconnects:
Usage: optional
Value type: <u32 array of bdfs>
Definition: Skip enumeration for the list of 32-bit BDFs.
- qcom,config-recovery:
Usage: optional
Value type : <bool>
Definition: Enable to notify the client driver for recovery when
config space is not accessible
- qcom, pcie-halt-feature-dis:
Usage: optional
Value type : <bool>
Definition: Disable PCIe Write and Read halt feature
==============
Root port node
==============

1
qcom/sdxlemur-pcie.dtsi
View file

@ -115,6 +115,7 @@
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,pcie-halt-feature-dis;
qcom,pcie-phy-ver = <1108>;
qcom,phy-status-offset = <0x1214>;