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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "ARM: dts: msm: populate the property to exclude reg-names for validation"
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qctecmdr
Gerrit - the friendly Code Review server
commit
4ac1baf4eb
5 changed files with 169 additions and 55 deletions
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@ -519,6 +519,14 @@ Optional properties:
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ordering block
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0: lower priority pipe has to be on the left for a given pair of pipes.
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1: priority have to be explicitly configured for a given pair of pipes.
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- qcom,sde-trusted-vm-env: Boolean property to indicate if the device
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driver is executing in a trusted VM
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- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum
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number of concurrent displays supported in the
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trusted vm environment
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- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which
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should be excluded from IO memory validation list
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in trusted vm environment
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Bus Scaling:
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- interconnects An array of 4 cell properties with the format of
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@ -711,6 +719,7 @@ Example:
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qcom,sde-has-idle-pc;
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qcom,fullsize-va-map;
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qcom,sde-has-dest-scaler;
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qcom,sde-max-trusted-vm-displays = <1>;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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qcom,sde-sspp-max-rects = <1 1 1 1
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@ -730,6 +739,7 @@ Example:
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qcom,sde-te2-off = <0x100>;
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qcom,sde-te-size = <0xffff>;
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qcom,sde-te2-size = <0xffff>;
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qcom,sde-trusted-vm-env;
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qcom,sde-wb-id = <2>;
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qcom,sde-wb-clk-ctrl = <0x2bc 16>;
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@ -162,6 +162,7 @@
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qcom,sde-pipe-order-version = <0x1>;
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qcom,sde-has-dim-layer;
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qcom,sde-has-dest-scaler;
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qcom,sde-max-trusted-vm-displays = <1>;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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@ -281,6 +282,33 @@
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <8350>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
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@ -293,6 +321,33 @@
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <5 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <8350>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
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@ -247,33 +247,6 @@
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<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <8350>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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&mdss_dsi1 {
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@ -287,34 +260,6 @@
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<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <8350>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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&mdss_dsi_phy0 {
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33
display/trustedvm-lahaina-sde-display.dtsi
Normal file
33
display/trustedvm-lahaina-sde-display.dtsi
Normal file
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@ -0,0 +1,33 @@
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#include "lahaina-sde-display-common.dtsi"
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&sde_dsi {
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clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>,
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<&clock_cpucc PCLK_MUX_0_CLK>,
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<&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>,
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<&clock_cpucc CPHY_PCLK_SRC_0_CLK>,
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<&clock_cpucc BYTECLK_SRC_0_CLK>,
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<&clock_cpucc PCLK_SRC_0_CLK>,
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<&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>,
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<&clock_cpucc SHADOW_PCLK_SRC_0_CLK>,
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<&clock_cpucc BYTECLK_MUX_1_CLK>,
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<&clock_cpucc PCLK_MUX_1_CLK>,
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<&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>,
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<&clock_cpucc CPHY_PCLK_SRC_1_CLK>,
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<&clock_cpucc BYTECLK_SRC_1_CLK>,
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<&clock_cpucc PCLK_SRC_1_CLK>,
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<&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>,
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<&clock_cpucc SHADOW_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"cphy_byte_clk0", "cphy_pixel_clk0",
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"src_byte_clk0", "src_pixel_clk0",
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"shadow_byte_clk0", "shadow_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"cphy_byte_clk1", "cphy_pixel_clk1",
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"src_byte_clk1", "src_pixel_clk1",
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"shadow_byte_clk1", "shadow_pixel_clk1";
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qcom,panel-te-source = <0>;
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};
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&mdss_mdp {
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connectors = <&sde_dsi>;
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};
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71
display/trustedvm-lahaina-sde.dtsi
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71
display/trustedvm-lahaina-sde.dtsi
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@ -0,0 +1,71 @@
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#include "lahaina-sde-common.dtsi"
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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
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&soc {
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/* dummy display clock provider */
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clock_cpucc: qcom,cpucc {
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compatible = "qcom,dummycc";
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clock-output-names = "cpucc_clocks";
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#clock-cells = <1>;
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};
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};
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&mdss_mdp {
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reg = <0x0ae00000 0x84000>,
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<0x0aeb0000 0x2008>,
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<0x0aeac000 0x800>,
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<0x0ae8f000 0x02c>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"sid_phys";
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qcom,sde-vm-exclude-reg-names = "sid_phys";
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qcom,sde-hw-version =<0x70000000>;
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clocks =
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<&clock_cpucc GCC_DISP_AHB_CLK>,
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<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
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<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
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<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
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<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&clock_cpucc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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qcom,sde-trusted-vm-env;
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};
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&mdss_dsi0 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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};
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&mdss_dsi1 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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};
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&mdss_dsi_phy0 {
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qcom,dsi-pll-in-trusted-vm;
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};
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&mdss_dsi_phy1 {
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qcom,dsi-pll-in-trusted-vm;
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};
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