mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 15:11:48 -04:00
Merge "ARM: dts: msm: Add UFS support for SA8155"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
4f22025022
9 changed files with 887 additions and 8 deletions
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@ -1,2 +1,27 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-pll-supply = <&pm8150_2_l8>;
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vdda-phy-max-microamp = <87100>;
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vdda-pll-max-microamp = <18300>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8150_1_l10>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm8150_1_s4>;
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vcc-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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status = "ok"
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};
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@ -344,6 +344,7 @@
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rpmh-regulator-gfxlvl {
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compatible = "qcom,rpmh-arc-regulator";
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qcom,resource-name = "gfx.lvl";
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VDD_GFX_LEVEL:
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S3C_LEVEL: pm8150_2_s3_level: regulator-pm8150-2-s3-level {
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regulator-name = "pm8150_2_s3_level";
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qcom,set = <RPMH_REGULATOR_SET_ALL>;
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@ -7,3 +7,23 @@
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qcom,msm-name = "SA8155 V1";
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qcom,msm-id = <362 0x10000>;
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};
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&scc {
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compatible = "qcom,sa8155-scc", "syscon";
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};
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&gcc {
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compatible = "qcom,sa8155-gcc", "syscon";
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};
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&videocc {
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compatible = "qcom,sa8155-videocc", "syscon";
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};
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&npucc {
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compatible = "qcom,sa8155-npucc", "syscon";
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};
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&camcc {
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compatible = "qcom,sa8155-camcc", "syscon";
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};
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@ -6,3 +6,23 @@
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qcom,msm-name = "SA8155 V2";
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qcom,msm-id = <362 0x20000>;
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};
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&scc {
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compatible = "qcom,sa8155-scc-v2", "syscon";
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};
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&gcc {
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compatible = "qcom,sa8155-gcc-v2", "syscon";
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};
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&videocc {
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compatible = "qcom,sa8155-videocc-v2", "syscon";
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};
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&npucc {
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compatible = "qcom,sa8155-npucc-v2", "syscon";
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};
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&camcc {
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compatible = "qcom,sa8155-camcc-v2", "syscon";
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};
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@ -55,3 +55,20 @@
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/* Add regulator nodes specific to SA8155 */
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#include "sa8155-regulator.dtsi"
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&gpucc {
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compatible = "qcom,sa8155-gpucc", "syscon";
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};
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&scc {
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vdd_scc_cx-supply = <&VDD_CX_LEVEL>;
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status = "ok"
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};
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&gpu_gx_gdsc {
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parent-supply = <&VDD_GFX_LEVEL>;
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};
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&ufsphy_mem {
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vdda-phy-supply = <&pm8150_2_l18>;
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};
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254
qcom/sm8150-gdsc.dtsi
Normal file
254
qcom/sm8150-gdsc.dtsi
Normal file
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@ -0,0 +1,254 @@
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&soc {
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/* GDSCs in Global CC */
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emac_gdsc: qcom,gdsc@106004 {
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compatible = "qcom,gdsc";
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regulator-name = "emac_gdsc";
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reg = <0x106004 0x4>;
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status = "disabled";
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};
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pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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regulator-name = "pcie_0_gdsc";
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reg = <0x16b004 0x4>;
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status = "disabled";
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};
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pcie_1_gdsc: qcom,gdsc@18d004 {
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compatible = "qcom,gdsc";
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regulator-name = "pcie_1_gdsc";
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reg = <0x18d004 0x4>;
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status = "disabled";
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};
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ufs_card_gdsc: qcom,gdsc@175004 {
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compatible = "qcom,gdsc";
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regulator-name = "ufs_card_gdsc";
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reg = <0x175004 0x4>;
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status = "disabled";
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};
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ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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regulator-name = "ufs_phy_gdsc";
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reg = <0x177004 0x4>;
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status = "disabled";
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};
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usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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regulator-name = "usb30_prim_gdsc";
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reg = <0x10f004 0x4>;
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status = "disabled";
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};
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usb30_sec_gdsc: qcom,gdsc@110004 {
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compatible = "qcom,gdsc";
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regulator-name = "usb30_sec_gdsc";
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reg = <0x110004 0x4>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
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reg = <0x17d040 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
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reg = <0x17d044 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
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reg = <0x17d048 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
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reg = <0x17d04c 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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reg = <0x17d050 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
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reg = <0x17d054 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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reg = <0x17d058 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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reg = <0x17d05c 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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reg = <0x17d060 0x4>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in Camera CC */
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bps_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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regulator-name = "bps_gdsc";
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reg = <0xad07004 0x4>;
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status = "disabled";
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};
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ipe_0_gdsc: qcom,gdsc@ad08004 {
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compatible = "qcom,gdsc";
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regulator-name = "ipe_0_gdsc";
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reg = <0xad08004 0x4>;
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status = "disabled";
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};
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ipe_1_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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regulator-name = "ipe_1_gdsc";
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reg = <0xad09004 0x4>;
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status = "disabled";
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};
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ife_0_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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regulator-name = "ife_0_gdsc";
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reg = <0xad0a004 0x4>;
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status = "disabled";
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};
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ife_1_gdsc: qcom,gdsc@ad0b004 {
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compatible = "qcom,gdsc";
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regulator-name = "ife_1_gdsc";
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reg = <0xad0b004 0x4>;
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status = "disabled";
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};
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titan_top_gdsc: qcom,gdsc@ad0c1bc {
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compatible = "qcom,gdsc";
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regulator-name = "titan_top_gdsc";
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reg = <0xad0c1bc 0x4>;
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status = "disabled";
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};
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/* GDSCs in Display CC */
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mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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regulator-name = "mdss_core_gdsc";
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reg = <0xaf03000 0x4>;
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qcom,support-hw-trigger;
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status = "disabled";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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};
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/* GDSCs in Graphics CC */
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gpu_cx_hw_ctrl: syscon@2c91540 {
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compatible = "syscon";
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reg = <0x2c91540 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@2c9106c {
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compatible = "qcom,gdsc";
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regulator-name = "gpu_cx_gdsc";
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reg = <0x2c9106c 0x4>;
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,skip-disable;
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qcom,gds-timeout = <500>;
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qcom,clk-dis-wait-val = <8>;
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mboxes = <&qmp_aop 0>;
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status = "disabled";
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};
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gpu_gx_domain_addr: syscon@2c91508 {
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compatible = "syscon";
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reg = <0x2c91508 0x4>;
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};
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gpu_gx_sw_reset: syscon@2c91008 {
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compatible = "syscon";
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reg = <0x2c91008 0x4>;
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};
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gpu_gx_gdsc: qcom,gdsc@2c9100c {
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compatible = "qcom,gdsc";
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regulator-name = "gpu_gx_gdsc";
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reg = <0x2c9100c 0x4>;
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domain-addr = <&gpu_gx_domain_addr>;
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sw-reset = <&gpu_gx_sw_reset>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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/* GDSCs in Video CC */
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mvsc_gdsc: qcom,gdsc@ab00814 {
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compatible = "qcom,gdsc";
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regulator-name = "mvsc_gdsc";
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reg = <0xab00814 0x4>;
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status = "disabled";
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};
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mvs0_gdsc: qcom,gdsc@ab00874 {
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compatible = "qcom,gdsc";
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regulator-name = "mvs0_gdsc";
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reg = <0xab00874 0x4>;
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status = "disabled";
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};
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mvs1_gdsc: qcom,gdsc@ab008b4 {
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compatible = "qcom,gdsc";
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regulator-name = "mvs1_gdsc";
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reg = <0xab008b4 0x4>;
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status = "disabled";
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};
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/* GDSCs in NPU CC */
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npu_core_gdsc: qcom,gdsc@9911028 {
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compatible = "qcom,gdsc";
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regulator-name = "npu_core_gdsc";
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reg = <0x9911028 0x4>;
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status = "disabled";
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};
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};
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@ -450,6 +450,7 @@
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rpmh-regulator-gfxlvl {
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compatible = "qcom,rpmh-arc-regulator";
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qcom,resource-name = "gfx.lvl";
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VDD_GFX_LEVEL:
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S2C_LEVEL: pm8150l_s2_level: regulator-pm8150l-s2-level {
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regulator-name = "pm8150l_s2_level";
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qcom,set = <RPMH_REGULATOR_SET_ALL>;
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|
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@ -5,3 +5,27 @@
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qcom,msm-name = "SM8150 V2";
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qcom,msm-id = <339 0x20000>;
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};
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&gcc {
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compatible = "qcom,sm8150-gcc-v2", "syscon";
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};
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&camcc {
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compatible = "qcom,sm8150-camcc-v2", "syscon";
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};
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&dispcc {
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compatible = "qcom,sm8150-dispcc-v2", "syscon";
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};
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&videocc {
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compatible = "qcom,sm8150-videocc-v2", "syscon";
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};
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&npucc {
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compatible = "qcom,sm8150-npucc-v2", "syscon";
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};
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&scc {
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compatible = "qcom,sm8150-scc-v2", "syscon";
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};
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|
|
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533
qcom/sm8150.dtsi
533
qcom/sm8150.dtsi
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|
@ -1,3 +1,14 @@
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-sm8150.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include <dt-bindings/clock/qcom,npucc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8150.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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@ -14,6 +25,7 @@
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
|
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serial0 = &uart2;
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};
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||||
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|
@ -673,6 +685,10 @@
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|||
<WAKE_TCS 3>,
|
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<CONTROL_TCS 1>;
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||||
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||||
apps_bcm_voter: bcm_voter {
|
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compatible = "qcom,bcm-voter";
|
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};
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||||
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rpmhcc: clock-controller {
|
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compatible = "qcom,sm8150-rpmh-clk";
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#clock-cells = <1>;
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||||
|
|
@ -699,26 +715,371 @@
|
|||
<ACTIVE_TCS 2>,
|
||||
<CONTROL_TCS 0>;
|
||||
|
||||
disp_bcm_voter: bcm_voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
aopcc: qcom,aopcc {
|
||||
compatible = "qcom,aop-qmp-clk";
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "qdss_clk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
compatible = "qcom,sm8150-gcc", "syscon";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
videocc: clock-controller@ab00000 {
|
||||
compatible = "qcom,sm8150-videocc", "syscon";
|
||||
reg = <0xab00000 0x10000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "cfg_ahb_clk", "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8150-camcc", "syscon";
|
||||
reg = <0xad00000 0x10000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "cfg_ahb_clk", "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,sm8150-dispcc", "syscon";
|
||||
reg = <0xaf00000 0x20000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "cfg_ahb_clk", "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
npucc: clock-controller@9910000 {
|
||||
compatible = "qcom,sm8150-npucc", "syscon";
|
||||
reg = <0x9910000 0x10000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_gdsc-supply = <&npu_core_gdsc>;
|
||||
clocks =
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_NPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_NPU_AXI_CLK>;
|
||||
clock-names =
|
||||
"bi_tcxo",
|
||||
"gcc_npu_gpll0_div_clk_src",
|
||||
"gcc_npu_gpll0_clk_src",
|
||||
"gcc_npu_axi_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpucc: clock-controller@2c90000 {
|
||||
compatible = "qcom,sm8150-gpucc", "syscon";
|
||||
reg = <0x2c90000 0x9000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
clocks =
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk";
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
scc: clock-controller@2b10000 {
|
||||
compatible = "qcom,sm8150-scc", "syscon";
|
||||
reg = <0x2b10000 0x30000>;
|
||||
vdd_scc_cx-supply = <&pm8150_l8_level>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpucc: syscon@182a0018 {
|
||||
compatible = "syscon";
|
||||
reg = <0x182a0000 0x4>;
|
||||
};
|
||||
|
||||
mccc: syscon@90b0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x90b0000 0x1000>;
|
||||
};
|
||||
|
||||
debugcc: debug-clock-controller@0 {
|
||||
compatible = "qcom,sm8150-debugcc";
|
||||
qcom,gcc = <&gcc>;
|
||||
qcom,videocc = <&videocc>;
|
||||
qcom,camcc = <&camcc>;
|
||||
qcom,dispcc = <&dispcc>;
|
||||
qcom,npucc = <&npucc>;
|
||||
qcom,gpucc = <&gpucc>;
|
||||
qcom,cpucc = <&cpucc>;
|
||||
qcom,mccc = <&mccc>;
|
||||
clock-names = "xo_clk_src";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
config_noc: interconnect@1500000 {
|
||||
reg = <0x1500000 0x7400>;
|
||||
compatible = "qcom,sm8150-config_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system_noc: interconnect@1620000 {
|
||||
reg = <0x1620000 0x19400>;
|
||||
compatible = "qcom,sm8150-system_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
camnoc_virt: interconnect@1630000 {
|
||||
compatible = "qcom,sm8150-camnoc_virt";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
ipa_virt: interconnect@1640000 {
|
||||
compatible = "qcom,sm8150-ipa_virt";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
reg = <0x16E0000 0xD080>;
|
||||
compatible = "qcom,sm8150-aggre1_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
reg = <0x1700000 0x3B100>;
|
||||
compatible = "qcom,sm8150-aggre2_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
compute_noc: interconnect@1710000 {
|
||||
compatible = "qcom,sm8150-compute_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1740000 {
|
||||
reg = <0x1740000 0x1C100>;
|
||||
compatible = "qcom,sm8150-mmss_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos", "disp";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
||||
};
|
||||
|
||||
dc_noc: interconnect@9160000 {
|
||||
reg = <0x9160000 0x3200>;
|
||||
compatible = "qcom,sm8150-dc_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@9680000 {
|
||||
reg = <0x9680000 0x3E200>;
|
||||
compatible = "qcom,sm8150-gem_noc";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos", "disp";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect@9690000 {
|
||||
compatible = "qcom,sm8150-mc_virt";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos", "disp";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
||||
};
|
||||
|
||||
|
||||
ufsphy_mem: ufsphy_mem@1d87000 {
|
||||
reg = <0x1d87000 0xda8>; /* PHY regs */
|
||||
reg-names = "phy_mem";
|
||||
#phy-cells = <0>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
|
||||
clock-names = "ref_clk_src",
|
||||
"ref_clk",
|
||||
"ref_aux_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
||||
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
||||
|
||||
resets = <&ufshc_mem 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufshc_mem: ufshc@1d84000 {
|
||||
compatible = "qcom,ufshc";
|
||||
reg = <0x1d84000 0x2500>,
|
||||
<0x1d90000 0x8000>;
|
||||
reg-names = "ufs_mem", "ufs_ice";
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&ufsphy_mem>;
|
||||
phy-names = "ufsphy";
|
||||
#reset-cells = <1>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
freq-table-hz =
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<37500000 300000000>,
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>;
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
||||
interconnect-names = "ufs-ddr", "cpu-ufs";
|
||||
|
||||
qcom,ufs-bus-bw,name = "ufshc_mem";
|
||||
qcom,ufs-bus-bw,num-cases = <26>;
|
||||
qcom,ufs-bus-bw,num-paths = <2>;
|
||||
qcom,ufs-bus-bw,vectors-KBps =
|
||||
/*
|
||||
* During HS G3 UFS runs at nominal voltage corner, vote
|
||||
* higher bandwidth to push other buses in the data path
|
||||
* to run at nominal to achieve max throughput.
|
||||
* 4GBps pushes BIMC to run at nominal.
|
||||
* 200MBps pushes CNOC to run at nominal.
|
||||
* Vote for half of this bandwidth for HS G3 1-lane.
|
||||
* For max bandwidth, vote high enough to push the buses
|
||||
* to run in turbo voltage corner.
|
||||
*/
|
||||
<0 0>, <0 0>, /* No vote */
|
||||
<922 0>, <1000 0>, /* PWM G1 */
|
||||
<1844 0>, <1000 0>, /* PWM G2 */
|
||||
<3688 0>, <1000 0>, /* PWM G3 */
|
||||
<7376 0>, <1000 0>, /* PWM G4 */
|
||||
<1844 0>, <1000 0>, /* PWM G1 L2 */
|
||||
<3688 0>, <1000 0>, /* PWM G2 L2 */
|
||||
<7376 0>, <1000 0>, /* PWM G3 L2 */
|
||||
<14752 0>, <1000 0>, /* PWM G4 L2 */
|
||||
<127796 0>, <1000 0>, /* HS G1 RA */
|
||||
<255591 0>, <1000 0>, /* HS G2 RA */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RA */
|
||||
<4194304 0>, <204800 0>, /* HS G4 RA */
|
||||
<255591 0>, <1000 0>, /* HS G1 RA L2 */
|
||||
<511181 0>, <1000 0>, /* HS G2 RA L2 */
|
||||
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
|
||||
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
|
||||
<149422 0>, <1000 0>, /* HS G1 RB */
|
||||
<298189 0>, <1000 0>, /* HS G2 RB */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RB */
|
||||
<4194304 0>, <204800 0>, /* HS G4 RB */
|
||||
<298189 0>, <1000 0>, /* HS G1 RB L2 */
|
||||
<596378 0>, <1000 0>, /* HS G2 RB L2 */
|
||||
/* As UFS working in HS G3 RB L2 mode, aggregated
|
||||
* bandwidth (AB) should take care of providing
|
||||
* optimum throughput requested. However, as tested,
|
||||
* in order to scale up CNOC clock, instantaneous
|
||||
* bindwidth (IB) needs to be given a proper value too.
|
||||
*/
|
||||
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
|
||||
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
|
||||
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
||||
|
||||
qcom,bus-vector-names = "MIN",
|
||||
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
||||
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
|
||||
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
|
||||
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
|
||||
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
|
||||
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
|
||||
"MAX";
|
||||
|
||||
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
status = "disabled";
|
||||
qos0 {
|
||||
mask = <0xf0>;
|
||||
vote = <44>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0x0f>;
|
||||
vote = <44>;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x00ac0000 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc 123>,
|
||||
<&gcc 124>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -729,7 +1090,7 @@
|
|||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00a90000 0x0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc 105>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "ok"
|
||||
};
|
||||
|
|
@ -1112,3 +1473,159 @@
|
|||
#include "sm8150-pm.dtsi"
|
||||
#include "sm8150-slpi-pinctrl.dtsi"
|
||||
#include "sm8150-smp2p.dtsi"
|
||||
#include "sm8150-gdsc.dtsi"
|
||||
|
||||
&emac_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_phy_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_card_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_prim_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_sec_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&bps_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ipe_0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ipe_1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&titan_top_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mdss_core_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_cx_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_gx_gdsc {
|
||||
parent-supply = <&VDD_GFX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvsc_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvs0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvs1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&npu_core_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue