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drivers: pinctrl: Add support to access tlmm spare registers

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Add support to read and write SPARE registers in TLMM block.

Change-Id: I6426b86510256983b509c5f48c2ab02f80b48ef8
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
This commit is contained in:
Mayank Grover 2021-03-11 16:37:45 +05:30 • committed by Gerrit - the friendly Code Review server
commit 51d46d049b
3 changed files with 57 additions and 1 deletions
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40
drivers/pinctrl/qcom/pinctrl-msm.c
View file

@ -37,6 +37,7 @@
#define MAX_NR_TILES 4
#define PS_HOLD_OFFSET 0x820
#define QUP_MASK GENMASK(5, 0)
#define SPARE_MASK GENMASK(15, 8)
/**
* struct msm_pinctrl - state for a pinctrl-msm device
@ -1505,6 +1506,45 @@ int msm_qup_read(unsigned int mode)
return -ENOENT;
}
int msm_spare_write(int spare_reg, u32 val)
{
u32 offset;
const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
int num_regs = msm_pinctrl_data->soc->nspare_regs;
if (!regs || spare_reg >= num_regs)
return -ENOENT;
offset = regs[spare_reg].offset;
if (offset != 0) {
writel_relaxed(val & SPARE_MASK,
msm_pinctrl_data->regs[0] + offset);
return 0;
}
return -ENOENT;
}
EXPORT_SYMBOL(msm_spare_write);
int msm_spare_read(int spare_reg)
{
u32 offset, val;
const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
int num_regs = msm_pinctrl_data->soc->nspare_regs;
if (!regs || spare_reg >= num_regs)
return -ENOENT;
offset = regs[spare_reg].offset;
if (offset != 0) {
val = readl_relaxed(msm_pinctrl_data->regs[0] + offset);
return val & SPARE_MASK;
}
return -ENOENT;
}
EXPORT_SYMBOL(msm_spare_read);
/*
* msm_gpio_mpm_wake_set - API to make interrupt wakeup capable
* @dev: Device corrsponding to pinctrl

12
drivers/pinctrl/qcom/pinctrl-msm.h
View file

@ -125,6 +125,16 @@ struct pinctrl_qup {
u32 offset;
};
/*
* struct msm_spare_tlmm - TLMM spare registers config
* @spare_reg: spare register number
* @offset: Offset of spare register
*/
struct msm_spare_tlmm {
int spare_reg;
u32 offset;
};
/**
* struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
* @gpio: The GPIOs that are wakeup capable
@ -169,6 +179,8 @@ struct msm_pinctrl_soc_data {
unsigned int n_no_wake_gpios;
struct pinctrl_qup *qup_regs;
unsigned int nqup_regs;
const struct msm_spare_tlmm *spare_regs;
unsigned int nspare_regs;
struct msm_dir_conn *dir_conn;
};

6
include/linux/pinctrl/qcom-pinctrl.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019,2021 The Linux Foundation. All rights reserved.
*/
#ifndef __LINUX_PINCTRL_MSM_H__
@ -15,4 +15,8 @@ int msm_qup_read(u32 mode);
/* API to write to mpm_wakeup registers */
int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable);
/* APIS to TLMM Spare registers */
int msm_spare_write(int spare_reg, u32 val);
int msm_spare_read(int spare_reg);
#endif /* __LINUX_PINCTRL_MSM_H__ */