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msm: kgsl: Create a6xx rgmu power ops

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This completely dissociates the power sequences from
the kgsl power controller for rgmu based targets and
makes them target specific.

Change-Id: I7f848ab507762ee6cdcfa6f64d07c84967a35bfa
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt 2020-04-22 19:55:40 -06:00
commit 51f932b1e3
8 changed files with 634 additions and 222 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/msm/adreno-gpulist.h
View file

@ -1382,7 +1382,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
.features = ADRENO_CONTENT_PROTECTION |
ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |
ADRENO_IFPC,
.gpudev = &adreno_a6xx_gpudev,
.gpudev = &adreno_a6xx_rgmu_gpudev,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_4K),
.bus_width = 32,

1
drivers/gpu/msm/adreno.h
View file

@ -906,6 +906,7 @@ extern struct adreno_gpudev adreno_a3xx_gpudev;
extern struct adreno_gpudev adreno_a5xx_gpudev;
extern struct adreno_gpudev adreno_a6xx_gpudev;
extern struct adreno_gpudev adreno_a6xx_gmu_gpudev;
extern struct adreno_gpudev adreno_a6xx_rgmu_gpudev;
extern int adreno_wake_nice;
extern unsigned int adreno_wake_timeout;

35
drivers/gpu/msm/adreno_a6xx.c
View file

@ -2712,3 +2712,38 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
.read_alwayson = a6xx_read_alwayson,
.power_ops = &a6xx_gmu_power_ops,
};
struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_rgmu_device_probe,
.start = a6xx_start,
.snapshot = a6xx_snapshot,
.init = a6xx_init,
.irq_handler = a6xx_irq_handler,
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,
.hw_isidle = a6xx_hw_isidle,
.iommu_fault_block = a6xx_iommu_fault_block,
.reset = a6xx_rgmu_restart,
.preemption_pre_ibsubmit = a6xx_preemption_pre_ibsubmit,
.preemption_post_ibsubmit = a6xx_preemption_post_ibsubmit,
.preemption_init = a6xx_preemption_init,
.preemption_schedule = a6xx_preemption_schedule,
.set_marker = a6xx_set_marker,
.preemption_context_init = a6xx_preemption_context_init,
.preemption_context_destroy = a6xx_preemption_context_destroy,
.sptprac_is_on = a6xx_sptprac_is_on,
.ccu_invalidate = a6xx_ccu_invalidate,
.perfcounter_update = a6xx_perfcounter_update,
#ifdef CONFIG_QCOM_KGSL_CORESIGHT
.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
#endif
.clk_set_options = a6xx_clk_set_options,
.read_alwayson = a6xx_read_alwayson,
.power_ops = &a6xx_rgmu_power_ops,
};

4
drivers/gpu/msm/adreno_a6xx.h
View file

@ -11,8 +11,10 @@
#include "a6xx_reg.h"
#include "adreno_a6xx_gmu.h"
#include "adreno_a6xx_rgmu.h"
extern const struct adreno_power_ops a6xx_gmu_power_ops;
extern const struct adreno_power_ops a6xx_rgmu_power_ops;
/**
* struct a6xx_device - Container for the a6xx_device
@ -20,6 +22,8 @@ extern const struct adreno_power_ops a6xx_gmu_power_ops;
struct a6xx_device {
/** @gmu: Container for the a6xx GMU device */
struct a6xx_gmu_device gmu;
/** @rgmu: Container for the a6xx rGMU device */
struct a6xx_rgmu_device rgmu;
/** @adreno_dev: Container for the generic adreno device */
struct adreno_device adreno_dev;
};

12
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -2706,7 +2706,7 @@ error:
return ret;
}
static void enable_gpu_irq(struct adreno_device *adreno_dev)
void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
@ -2717,7 +2717,7 @@ static void enable_gpu_irq(struct adreno_device *adreno_dev)
trace_kgsl_irq(device, 1);
}
static void disable_gpu_irq(struct adreno_device *adreno_dev)
void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
@ -2769,11 +2769,11 @@ static int a6xx_gpu_boot(struct adreno_device *adreno_dev)
/* Clear FSR here in case it is set from a previous pagefault */
kgsl_mmu_clear_fsr(&device->mmu);
enable_gpu_irq(adreno_dev);
a6xx_enable_gpu_irq(adreno_dev);
ret = a6xx_rb_start(adreno_dev);
if (ret) {
disable_gpu_irq(adreno_dev);
a6xx_disable_gpu_irq(adreno_dev);
goto oob_clear;
}
@ -2953,7 +2953,7 @@ static int a6xx_power_off(struct adreno_device *adreno_dev)
a6xx_gmu_oob_clear(device, oob_gpu);
no_gx_power:
disable_gpu_irq(adreno_dev);
a6xx_disable_gpu_irq(adreno_dev);
a6xx_gmu_power_off(adreno_dev);
@ -3157,7 +3157,7 @@ int a6xx_gmu_restart(struct kgsl_device *device)
a6xx_hfi_stop(adreno_dev);
disable_gpu_irq(adreno_dev);
a6xx_disable_gpu_irq(adreno_dev);
/* Hard reset the gmu and gpu */
a6xx_gmu_suspend(adreno_dev);

14
drivers/gpu/msm/adreno_a6xx_gmu.h
View file

@ -274,4 +274,18 @@ int a6xx_gmu_device_probe(struct platform_device *pdev,
* Return: 0 on success or negative error on failure
*/
int a6xx_gmu_restart(struct kgsl_device *device);
/**
* a6xx_enable_gpu_irq - Enable gpu interrupt
* @adreno_dev: Pointer to the adreno device
*/
void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev);
/**
* a6xx_disable_gpu_irq - Disable gpu interrupt
* @adreno_dev: Pointer to the adreno device
*/
void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev);
#endif

755
drivers/gpu/msm/adreno_a6xx_rgmu.c
View file

File diff suppressed because it is too large Load diff

33
drivers/gpu/msm/adreno_a6xx_rgmu.h
View file

@ -15,6 +15,15 @@
#define MAX_RGMU_CLKS 8
enum {
/* @RGMU_PRIV_FIRST_BOOT_DONE: The very first ggpu boot is done */
RGMU_PRIV_FIRST_BOOT_DONE,
/* @RGMU_PRIV_GPU_STARTED: GPU has been started */
RGMU_PRIV_GPU_STARTED,
/* @RGMU_PRIV_PM_SUSPEND: The rgmu driver is suspended */
RGMU_PRIV_PM_SUSPEND,
};
/**
* struct a6xx_rgmu_device - rGMU device structure
* @ver: RGMU firmware version
@ -47,8 +56,28 @@ struct a6xx_rgmu_device {
struct clk *rgmu_clk;
unsigned int idle_level;
unsigned int fault_count;
/** @fault: to track whether we encountered a rgmu fault */
bool fault;
/** @flags: rgmu internal flags */
unsigned long flags;
};
#define A6XX_RGMU_DEVICE(_a) ((struct a6xx_rgmu_device *)((_a)->gmu_core.ptr))
/**
* a6xx_rgmu_device_probe - Probe a6xx rgmu resources
* @pdev: Pointer to the platform device
* @chipid: Chipid of the target
* @gpucore: Pointer to the gpucore
*
* The target specific probe function for rgmu based a6xx targets.
*/
int a6xx_rgmu_device_probe(struct platform_device *pdev,
u32 chipid, const struct adreno_gpu_core *gpucore);
#endif /* __ADRENO_A6XX_RGMU_H */
/**
* a6xx_rgmu_restart - Reset and restart the rgmu
* @device: Pointer to the kgsl device
*
* Return: 0 on success or negative error on failure
*/
int a6xx_rgmu_restart(struct kgsl_device *device);
#endif