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ARM: dts: msm: Add jtag_mm nodes for monaco

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Enable jtag_mm nodes to support cpu etm save/restore feature.

Change-Id: I840df2bd17547432123dac84b10b8b7bf32b324c
This commit is contained in:
Huixian Ma 2021-05-11 19:01:21 +08:00 • committed by Gerrit - the friendly Code Review server
commit 5375dd3fdb
1 changed files with 44 additions and 0 deletions
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44
qcom/monaco.dtsi
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@ -1122,6 +1122,50 @@
};
};
jtag_mm0: jtagmm@9040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9040000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@9140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9140000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@9240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9240000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@9340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9340000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
clk_virt: interconnect {
compatible = "qcom,monaco-clk_virt";
#interconnect-cells = <1>;