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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: qcom: add GDSC devices for Lahaina
Add global distributed switch controller (GDSC) device nodes for the GDSCs managed by the application processor on Lahaina. Change-Id: I63d013808d7752dca38e941cd6db7eb85cc01d9c
This commit is contained in:
David Collins
Gerrit - the friendly Code Review server
parent
c049f2cdf6
commit
5376afb903
3 changed files with 270 additions and 2 deletions
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@ -372,7 +372,7 @@
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pm8350c_s8_level-parent-supply = <&VDD_MXA_LEVEL>;
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pm8350c_s8_level_ao-parent-supply = <&VDD_MXA_LEVEL_AO>;
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VDD_MMCX_LEVEL: S8C_LEVEL:
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VDD_MMCX_LEVEL: S8C_LEVEL: VDD_MM_LEVEL:
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pm8350c_s8_level: regulator-pm8350c-s8-level {
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regulator-name = "pm8350c_s8_level";
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qcom,set = <RPMH_REGULATOR_SET_ALL>;
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@ -386,7 +386,7 @@
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regulator-always-on;
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};
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VDD_MMCX_LEVEL_AO: S8C_LEVEL_AO:
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VDD_MMCX_LEVEL_AO: S8C_LEVEL_AO: VDD_MM_LEVEL_AO:
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pm8350c_s8_level_ao: regulator-pm8350c-s8-level-ao {
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regulator-name = "pm8350c_s8_level_ao";
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qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
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@ -15,6 +15,9 @@
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limit-tx-hs-gear = <1>;
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limit-rx-hs-gear = <1>;
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8350_l7>;
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vcc-max-microamp = <800000>;
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@ -80,3 +83,7 @@
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dr_mode = "peripheral";
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};
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};
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&gpu_cc_cx_gdsc {
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qcom,gds-timeout = <5000>;
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};
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@ -548,6 +548,267 @@
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#reset-cells = <1>;
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};
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/* CAM_CC GDSCs */
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cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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reg = <0xad07004 0x4>;
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regulator-name = "cam_cc_bps_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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reg = <0xad0a004 0x4>;
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regulator-name = "cam_cc_ife_0_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {
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compatible = "qcom,gdsc";
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reg = <0xad0b004 0x4>;
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regulator-name = "cam_cc_ife_1_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {
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compatible = "qcom,gdsc";
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reg = <0xad0b070 0x4>;
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regulator-name = "cam_cc_ife_2_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {
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compatible = "qcom,gdsc";
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reg = <0xad08004 0x4>;
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regulator-name = "cam_cc_ipe_0_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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cam_cc_sbi_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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reg = <0xad09004 0x4>;
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regulator-name = "cam_cc_sbi_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {
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compatible = "qcom,gdsc";
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reg = <0xad0c120 0x4>;
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regulator-name = "cam_cc_titan_top_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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/* DISP_CC GDSCs */
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disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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reg = <0xaf03000 0x4>;
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regulator-name = "disp_cc_mdss_core_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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/* GCC GDSCs */
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gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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reg = <0x16b004 0x4>;
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regulator-name = "gcc_pcie_0_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
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compatible = "qcom,gdsc";
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reg = <0x18d004 0x4>;
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regulator-name = "gcc_pcie_1_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_ufs_card_gdsc: qcom,gdsc@175004 {
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compatible = "qcom,gdsc";
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reg = <0x175004 0x4>;
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regulator-name = "gcc_ufs_card_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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reg = <0x177004 0x4>;
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regulator-name = "gcc_ufs_phy_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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reg = <0x10f004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_usb30_sec_gdsc: qcom,gdsc@110004 {
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compatible = "qcom,gdsc";
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reg = <0x110004 0x4>;
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regulator-name = "gcc_usb30_sec_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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reg = <0x17d050 0x4>;
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regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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};
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gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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reg = <0x17d058 0x4>;
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regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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};
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gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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reg = <0x17d054 0x4>;
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regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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};
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gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
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compatible = "qcom,gdsc";
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reg = <0x17d06c 0x4>;
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regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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};
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/* GPU_CC GDSCs */
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gpu_cc_cx_hw_ctrl: syscon@3d91540 {
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compatible = "syscon";
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reg = <0x3d91540 0x4>;
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};
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gpu_cc_cx_gdsc: qcom,gdsc@3d9106c {
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compatible = "qcom,gdsc";
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reg = <0x3d9106c 0x4>;
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regulator-name = "gpu_cc_cx_gdsc";
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hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,no-status-check-on-disable;
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qcom,clk-dis-wait-val = <8>;
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qcom,gds-timeout = <500>;
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qcom,retain-regs;
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};
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gpu_cc_gx_domain_addr: syscon@3d9158c {
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compatible = "syscon";
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reg = <0x3d9158c 0x4>;
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};
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gpu_cc_gx_sw_reset: syscon@3d91008 {
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compatible = "syscon";
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reg = <0x3d91008 0x4>;
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};
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gpu_cc_gx_gdsc: qcom,gdsc@3d9100c {
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compatible = "qcom,gdsc";
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reg = <0x3d9100c 0x4>;
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regulator-name = "gpu_cc_gx_gdsc";
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domain-addr = <&gpu_cc_gx_domain_addr>;
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sw-reset = <&gpu_cc_gx_sw_reset>;
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parent-supply = <&VDD_GFX_LEVEL>;
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vdd_parent-supply = <&VDD_GFX_LEVEL>;
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qcom,reset-aon-logic;
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qcom,retain-regs;
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};
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/* VIDEO_CC GDSCs */
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video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {
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compatible = "qcom,gdsc";
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reg = <0xabf0d18 0x4>;
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regulator-name = "video_cc_mvs0_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {
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compatible = "qcom,gdsc";
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reg = <0xabf0bf8 0x4>;
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regulator-name = "video_cc_mvs0c_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {
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compatible = "qcom,gdsc";
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reg = <0xabf0d98 0x4>;
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regulator-name = "video_cc_mvs1_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {
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compatible = "qcom,gdsc";
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reg = <0xabf0c98 0x4>;
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regulator-name = "video_cc_mvs1c_gdsc";
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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vdd_parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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};
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cache-controller@9200000 {
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compatible = "qcom,lahaina-llcc", "qcom,llcc-v2";
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reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
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