mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 12:25:00 -04:00
Merge "dt-bindings: clk: Remove unused cpuss clocks for Lahaina"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
5490b09d03
2 changed files with 179 additions and 273 deletions
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@ -177,13 +177,6 @@ static const struct clk_parent_data gcc_parent_data_0[] = {
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct clk_parent_data gcc_parent_data_0_ao[] = {
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{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
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{ .hw = &gcc_gpll0.clkr.hw },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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@ -591,30 +584,6 @@ static struct clk_dummy usb3_uni_phy_sec_gcc_usb30_pipe_clk = {
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},
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};
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static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
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F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
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{ }
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};
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static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
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.cmd_rcgr = 0x4800c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
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.enable_safe_config = true,
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.flags = HW_CLK_CTRL_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_ahb_clk_src",
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.parent_data = gcc_parent_data_0_ao,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
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F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
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F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
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@ -1816,21 +1785,6 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
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},
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};
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static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
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.reg = 0x48024,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_cpuss_ahb_postdiv_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
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.reg = 0xf050,
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.shift = 0,
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@ -2137,26 +2091,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
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},
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};
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static struct clk_branch gcc_cpuss_ahb_clk = {
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.halt_reg = 0x48000,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x48000,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x52000,
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.enable_mask = BIT(21),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_ahb_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_ddrss_gpu_axi_clk = {
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.halt_reg = 0x71154,
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.halt_check = BRANCH_HALT_SKIP,
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@ -3353,26 +3287,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
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},
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};
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static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
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.halt_reg = 0x48178,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x48178,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x52000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_sys_noc_cpuss_ahb_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_throttle_pcie_ahb_clk = {
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.halt_reg = 0x9044,
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.halt_check = BRANCH_HALT,
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@ -4159,9 +4073,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
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[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
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[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
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[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
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[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
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[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
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[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
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[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
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[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
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[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
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@ -4273,7 +4184,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
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[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
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[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
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[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
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[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
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[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
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[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
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[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H
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@ -36,188 +36,184 @@
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#define GCC_CAMERA_XO_CLK 24
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
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#define GCC_CPUSS_AHB_CLK 27
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#define GCC_CPUSS_AHB_CLK_SRC 28
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 29
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#define GCC_DDRSS_GPU_AXI_CLK 30
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 31
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#define GCC_DISP_AHB_CLK 32
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#define GCC_DISP_HF_AXI_CLK 33
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#define GCC_DISP_SF_AXI_CLK 34
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#define GCC_DISP_XO_CLK 35
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#define GCC_GP1_CLK 36
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#define GCC_GP1_CLK_SRC 37
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#define GCC_GP2_CLK 38
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#define GCC_GP2_CLK_SRC 39
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#define GCC_GP3_CLK 40
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#define GCC_GP3_CLK_SRC 41
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#define GCC_GPLL0 42
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#define GCC_GPLL0_OUT_EVEN 43
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#define GCC_GPLL4 44
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#define GCC_GPLL9 45
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#define GCC_GPU_CFG_AHB_CLK 46
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#define GCC_GPU_GPLL0_CLK_SRC 47
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 48
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#define GCC_GPU_IREF_EN 49
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#define GCC_GPU_MEMNOC_GFX_CLK 50
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#define GCC_GPU_SNOC_DVM_GFX_CLK 51
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#define GCC_PCIE0_PHY_RCHNG_CLK 52
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#define GCC_PCIE1_PHY_RCHNG_CLK 53
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#define GCC_PCIE_0_AUX_CLK 54
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#define GCC_PCIE_0_AUX_CLK_SRC 55
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#define GCC_PCIE_0_CFG_AHB_CLK 56
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#define GCC_PCIE_0_CLKREF_EN 57
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#define GCC_PCIE_0_MSTR_AXI_CLK 58
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 59
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#define GCC_PCIE_0_PIPE_CLK 60
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#define GCC_PCIE_0_PIPE_CLK_SRC 61
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#define GCC_PCIE_0_SLV_AXI_CLK 62
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 63
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#define GCC_PCIE_1_AUX_CLK 64
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#define GCC_PCIE_1_AUX_CLK_SRC 65
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#define GCC_PCIE_1_CFG_AHB_CLK 66
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#define GCC_PCIE_1_CLKREF_EN 67
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#define GCC_PCIE_1_MSTR_AXI_CLK 68
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 69
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#define GCC_PCIE_1_PIPE_CLK 70
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#define GCC_PCIE_1_PIPE_CLK_SRC 71
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#define GCC_PCIE_1_SLV_AXI_CLK 72
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 73
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#define GCC_PDM2_CLK 74
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#define GCC_PDM2_CLK_SRC 75
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#define GCC_PDM_AHB_CLK 76
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#define GCC_PDM_XO4_CLK 77
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 78
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 79
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#define GCC_QMIP_DISP_AHB_CLK 80
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 82
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 83
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#define GCC_QUPV3_WRAP0_CORE_CLK 84
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#define GCC_QUPV3_WRAP0_S0_CLK 85
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 86
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#define GCC_QUPV3_WRAP0_S1_CLK 87
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 88
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#define GCC_QUPV3_WRAP0_S2_CLK 89
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 90
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#define GCC_QUPV3_WRAP0_S3_CLK 91
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 92
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#define GCC_QUPV3_WRAP0_S4_CLK 93
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 94
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#define GCC_QUPV3_WRAP0_S5_CLK 95
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 96
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#define GCC_QUPV3_WRAP0_S6_CLK 97
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 98
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#define GCC_QUPV3_WRAP0_S7_CLK 99
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 100
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 101
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#define GCC_QUPV3_WRAP1_CORE_CLK 102
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#define GCC_QUPV3_WRAP1_S0_CLK 103
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 104
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#define GCC_QUPV3_WRAP1_S1_CLK 105
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 106
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#define GCC_QUPV3_WRAP1_S2_CLK 107
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 108
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#define GCC_QUPV3_WRAP1_S3_CLK 109
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 110
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#define GCC_QUPV3_WRAP1_S4_CLK 111
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 112
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#define GCC_QUPV3_WRAP1_S5_CLK 113
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 114
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 115
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#define GCC_QUPV3_WRAP2_CORE_CLK 116
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#define GCC_QUPV3_WRAP2_S0_CLK 117
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 118
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#define GCC_QUPV3_WRAP2_S1_CLK 119
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 120
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#define GCC_QUPV3_WRAP2_S2_CLK 121
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 122
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#define GCC_QUPV3_WRAP2_S3_CLK 123
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 124
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#define GCC_QUPV3_WRAP2_S4_CLK 125
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 126
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#define GCC_QUPV3_WRAP2_S5_CLK 127
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 128
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 129
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 130
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 131
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 132
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 133
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 134
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#define GCC_SDCC2_AHB_CLK 135
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#define GCC_SDCC2_APPS_CLK 136
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#define GCC_SDCC2_APPS_CLK_SRC 137
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#define GCC_SDCC4_AHB_CLK 138
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#define GCC_SDCC4_APPS_CLK 139
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#define GCC_SDCC4_APPS_CLK_SRC 140
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 141
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#define GCC_THROTTLE_PCIE_AHB_CLK 142
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#define GCC_UFS_1_CLKREF_EN 143
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#define GCC_UFS_CARD_AHB_CLK 144
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#define GCC_UFS_CARD_AXI_CLK 145
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#define GCC_UFS_CARD_AXI_CLK_SRC 146
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#define GCC_UFS_CARD_AXI_HW_CTL_CLK 147
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#define GCC_UFS_CARD_ICE_CORE_CLK 148
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 149
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#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 150
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#define GCC_UFS_CARD_PHY_AUX_CLK 151
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 152
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#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 153
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 154
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 155
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 156
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 157
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 159
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 160
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 161
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#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 162
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#define GCC_UFS_PHY_AHB_CLK 163
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#define GCC_UFS_PHY_AXI_CLK 164
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#define GCC_UFS_PHY_AXI_CLK_SRC 165
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 166
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#define GCC_UFS_PHY_ICE_CORE_CLK 167
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 168
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 169
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#define GCC_UFS_PHY_PHY_AUX_CLK 170
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 171
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 172
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 173
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 174
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 175
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 176
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 177
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 178
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 179
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 180
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 181
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#define GCC_USB30_PRIM_MASTER_CLK 182
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 183
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 184
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 185
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 186
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#define GCC_USB30_PRIM_SLEEP_CLK 187
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#define GCC_USB30_SEC_MASTER_CLK 188
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#define GCC_USB30_SEC_MASTER_CLK_SRC 189
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 190
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 191
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 192
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#define GCC_USB30_SEC_SLEEP_CLK 193
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#define GCC_USB3_PRIM_PHY_AUX_CLK 194
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 197
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 198
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#define GCC_USB3_SEC_CLKREF_EN 199
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#define GCC_USB3_SEC_PHY_AUX_CLK 200
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 201
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 202
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#define GCC_USB3_SEC_PHY_PIPE_CLK 203
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 204
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#define GCC_VIDEO_AHB_CLK 205
|
||||
#define GCC_VIDEO_AXI0_CLK 206
|
||||
#define GCC_VIDEO_AXI1_CLK 207
|
||||
#define GCC_VIDEO_XO_CLK 208
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 27
|
||||
#define GCC_DDRSS_PCIE_SF_TBU_CLK 28
|
||||
#define GCC_DISP_AHB_CLK 29
|
||||
#define GCC_DISP_HF_AXI_CLK 30
|
||||
#define GCC_DISP_SF_AXI_CLK 31
|
||||
#define GCC_DISP_XO_CLK 32
|
||||
#define GCC_GP1_CLK 33
|
||||
#define GCC_GP1_CLK_SRC 34
|
||||
#define GCC_GP2_CLK 35
|
||||
#define GCC_GP2_CLK_SRC 36
|
||||
#define GCC_GP3_CLK 37
|
||||
#define GCC_GP3_CLK_SRC 38
|
||||
#define GCC_GPLL0 39
|
||||
#define GCC_GPLL0_OUT_EVEN 40
|
||||
#define GCC_GPLL4 41
|
||||
#define GCC_GPLL9 42
|
||||
#define GCC_GPU_CFG_AHB_CLK 43
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 44
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 45
|
||||
#define GCC_GPU_IREF_EN 46
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 47
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 48
|
||||
#define GCC_PCIE0_PHY_RCHNG_CLK 49
|
||||
#define GCC_PCIE1_PHY_RCHNG_CLK 50
|
||||
#define GCC_PCIE_0_AUX_CLK 51
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 52
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 53
|
||||
#define GCC_PCIE_0_CLKREF_EN 54
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 55
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 56
|
||||
#define GCC_PCIE_0_PIPE_CLK 57
|
||||
#define GCC_PCIE_0_PIPE_CLK_SRC 58
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 59
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 60
|
||||
#define GCC_PCIE_1_AUX_CLK 61
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 62
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 63
|
||||
#define GCC_PCIE_1_CLKREF_EN 64
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 65
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66
|
||||
#define GCC_PCIE_1_PIPE_CLK 67
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 68
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 69
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70
|
||||
#define GCC_PDM2_CLK 71
|
||||
#define GCC_PDM2_CLK_SRC 72
|
||||
#define GCC_PDM_AHB_CLK 73
|
||||
#define GCC_PDM_XO4_CLK 74
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 76
|
||||
#define GCC_QMIP_DISP_AHB_CLK 77
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 78
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 79
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 80
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 81
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 82
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 83
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 84
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 85
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 86
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 87
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 88
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 89
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 90
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 91
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 92
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 93
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 94
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 95
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 96
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 97
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 98
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 99
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 100
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 101
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 102
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 103
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 104
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 105
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 106
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 107
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 108
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 109
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 110
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 111
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 112
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 113
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 114
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 115
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 116
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 117
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 118
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 119
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 120
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 121
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 122
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 123
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 124
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 125
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 126
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 127
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 128
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 129
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 130
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 131
|
||||
#define GCC_SDCC2_AHB_CLK 132
|
||||
#define GCC_SDCC2_APPS_CLK 133
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 134
|
||||
#define GCC_SDCC4_AHB_CLK 135
|
||||
#define GCC_SDCC4_APPS_CLK 136
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 137
|
||||
#define GCC_THROTTLE_PCIE_AHB_CLK 138
|
||||
#define GCC_UFS_1_CLKREF_EN 139
|
||||
#define GCC_UFS_CARD_AHB_CLK 140
|
||||
#define GCC_UFS_CARD_AXI_CLK 141
|
||||
#define GCC_UFS_CARD_AXI_CLK_SRC 142
|
||||
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 143
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK 144
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 145
|
||||
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 146
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK 147
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 148
|
||||
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 149
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 150
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 151
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 152
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 153
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 154
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 155
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 156
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 157
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 158
|
||||
#define GCC_UFS_PHY_AHB_CLK 159
|
||||
#define GCC_UFS_PHY_AXI_CLK 160
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 161
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 162
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 163
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 164
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 165
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 166
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 168
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 169
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 170
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 171
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 172
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 173
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 174
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 175
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 176
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 177
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 178
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 179
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 180
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 181
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 182
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 183
|
||||
#define GCC_USB30_SEC_MASTER_CLK 184
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 185
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 186
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 187
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 188
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 189
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 190
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 191
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 192
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 193
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 194
|
||||
#define GCC_USB3_SEC_CLKREF_EN 195
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 196
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 197
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 198
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 199
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 200
|
||||
#define GCC_VIDEO_AHB_CLK 201
|
||||
#define GCC_VIDEO_AXI0_CLK 202
|
||||
#define GCC_VIDEO_AXI1_CLK 203
|
||||
#define GCC_VIDEO_XO_CLK 204
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
|
|
|
|||
Loading…
Reference in a new issue