mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 16:16:15 -04:00
Merge "ARM: dts: msm: Add RSC device bindings for Shima"
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qctecmdr
Gerrit - the friendly Code Review server
commit
58642255ff
3 changed files with 245 additions and 0 deletions
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@ -7,6 +7,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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};
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};
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184
qcom/shima-pm.dtsi
Normal file
184
qcom/shima-pm.dtsi
Normal file
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@ -0,0 +1,184 @@
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&soc {
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qcom,lpm-levels {
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compatible = "qcom,lpm-levels";
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,pm-cluster@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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idle-state-name = "L3";
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qcom,clstr-tmr-add = <1000>;
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qcom,psci-mode-shift = <4>;
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qcom,psci-mode-mask = <0xfff>;
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CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "l3-wfi";
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entry-latency-us = <660>;
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exit-latency-us = <600>;
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min-residency-us = <1260>;
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arm,psci-suspend-param = <0x10>;
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qcom,psci-mode = <0x1>;
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};
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CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "l3-pc";
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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arm,psci-suspend-param = <0x40>;
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qcom,psci-mode = <0x4>;
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qcom,is-reset;
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qcom,min-child-idx = <2>;
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};
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CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */
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reg = <2>;
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compatible = "arm,idle-state";
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idle-state-name = "cx-off";
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entry-latency-us = <3263>;
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exit-latency-us = <4562>;
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min-residency-us = <8467>;
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arm,psci-suspend-param = <0x2240>;
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qcom,psci-mode = <0x224>;
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qcom,is-reset;
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qcom,notify-rpm;
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qcom,min-child-idx = <2>;
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};
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LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */
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reg = <3>;
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compatible = "arm,idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3638>;
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exit-latency-us = <6562>;
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min-residency-us = <9826>;
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arm,psci-suspend-param = <0xc240>;
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qcom,psci-mode = <0xc24>;
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qcom,is-reset;
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qcom,notify-rpm;
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qcom,min-child-idx = <2>;
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};
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qcom,pm-cpu@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,psci-mode-shift = <0>;
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qcom,psci-mode-mask = <0xf>;
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qcom,ref-stddev = <500>;
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qcom,tmr-add = <1000>;
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qcom,ref-premature-cnt = <1>;
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qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
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SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "wfi";
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entry-latency-us = <61>;
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exit-latency-us = <60>;
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min-residency-us = <121>;
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arm,psci-suspend-param = <0x1>;
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qcom,psci-cpu-mode = <0x1>;
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};
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SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <549>;
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exit-latency-us = <901>;
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min-residency-us = <1774>;
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arm,psci-suspend-param = <0x40000003>;
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qcom,psci-cpu-mode = <0x3>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */
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reg = <2>;
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <4001>;
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arm,psci-suspend-param = <0x40000004>;
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qcom,psci-cpu-mode = <0x4>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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};
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qcom,pm-cpu@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,psci-mode-shift = <0>;
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qcom,psci-mode-mask = <0xf>;
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qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
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GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "wfi";
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entry-latency-us = <55>;
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exit-latency-us = <66>;
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min-residency-us = <121>;
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arm,psci-suspend-param = <0x1>;
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qcom,psci-cpu-mode = <0x1>;
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};
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GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <523>;
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exit-latency-us = <1244>;
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min-residency-us = <2207>;
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arm,psci-suspend-param = <0x40000003>;
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qcom,psci-cpu-mode = <0x3>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */
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reg = <2>;
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <5555>;
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arm,psci-suspend-param = <0x40000004>;
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qcom,psci-cpu-mode = <0x4>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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};
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};
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};
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rpmh-master-stats@b221200 {
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compatible = "qcom,rpmh-master-stats-v1";
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reg = <0xb221200 0x60>;
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};
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soc-sleep-stats@c3f0000 {
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compatible = "qcom,rpmh-sleep-stats";
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reg = <0xc3f0000 0x400>;
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};
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ddr-stats@c300000 {
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compatible = "qcom,ddr-stats";
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reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
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reg-names = "phys_addr_base", "offset_addr";
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};
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};
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@ -7,6 +7,7 @@
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#include <dt-bindings/clock/qcom,videocc-shima.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Shima";
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@ -31,6 +32,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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@ -53,6 +55,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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@ -69,6 +72,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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@ -85,6 +89,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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@ -101,6 +106,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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@ -117,6 +123,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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@ -133,6 +140,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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@ -149,6 +157,7 @@
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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@ -324,6 +333,11 @@
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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@ -335,6 +349,19 @@
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,shima-pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
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qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
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<55 306 4>, <59 312 3>, <62 374 2>,
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<64 434 2>, <66 438 3>, <69 86 1>,
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<70 520 54>, <124 609 31>, <155 63 1>,
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<156 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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@ -772,9 +799,42 @@
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x18200000 0x10000>,
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<0x18210000 0x10000>,
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<0x18220000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>;
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>;
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};
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};
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#include "shima-pinctrl.dtsi"
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#include "shima-pm.dtsi"
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#include "shima-stub-regulator.dtsi"
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#include "shima-gdsc.dtsi"
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#include "shima-ion.dtsi"
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