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Merge "mmc: sdhci-msm: Update DDR_CONFIG reg with HSR value if supplied"

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This commit is contained in:
qctecmdr 2020-07-21 09:43:26 -07:00 • committed by Gerrit - the friendly Code Review server
commit 58797d8685
1 changed files with 44 additions and 5 deletions
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49
drivers/mmc/host/sdhci-msm.c
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@ -14,6 +14,7 @@
#include <linux/interconnect.h>
#include <linux/iopoll.h>
#include <linux/regulator/consumer.h>
#include <linux/pinctrl/consumer.h>
#include "sdhci-pltfm.h"
#include "cqhci.h"
@ -1143,7 +1144,13 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
ddr_cfg_offset = msm_offset->core_ddr_config;
else
ddr_cfg_offset = msm_offset->core_ddr_config_old;
writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
if (msm_host->dll_hsr->ddr_config)
config = msm_host->dll_hsr->ddr_config;
else
config = DDR_CONFIG_POR_VAL;
writel_relaxed(config, host->ioaddr + ddr_cfg_offset);
if (mmc->ios.enhanced_strobe) {
config = readl_relaxed(host->ioaddr +
@ -1169,9 +1176,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
goto out;
}
config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
config |= CORE_PWRSAVE_DLL;
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
/*
* Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
* When MCLK is gated OFF, it is not gated for less than 0.5us
* and MCLK must be switched on for at-least 1us before DATA
* starts coming. Controllers with 14lpp and later tech DLL cannot
* guarantee above requirement. So PWRSAVE_DLL should not be
* turned on for host controllers using this DLL.
*/
if (!msm_host->use_14lpp_dll_reset) {
config = readl_relaxed(host->ioaddr +
msm_offset->core_vendor_spec3);
config |= CORE_PWRSAVE_DLL;
writel_relaxed(config, host->ioaddr +
msm_offset->core_vendor_spec3);
}
/*
* Drain writebuffer to ensure above DLL calibration
@ -1481,6 +1500,20 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
sdhci_msm_hs400(host, &mmc->ios);
}
/* Apply active/sleep pin config based on bus on/off state */
static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
{
struct platform_device *pdev = msm_host->pdev;
int ret;
if (level)
ret = pinctrl_pm_select_default_state(&pdev->dev);
else
ret = pinctrl_pm_select_sleep_state(&pdev->dev);
return ret;
}
#define MAX_PROP_SIZE 32
static int sdhci_msm_dt_parse_vreg_info(struct device *dev,
struct sdhci_msm_reg_data **vreg_data, const char *vreg_name)
@ -2057,6 +2090,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
if (!ret)
ret = sdhci_msm_set_vdd_io_vol(msm_host,
VDD_IO_HIGH, 0);
if (!ret)
ret = sdhci_msm_set_pincfg(msm_host, true);
if (ret)
irq_ack |= CORE_PWRCTL_BUS_FAIL;
else
@ -2072,6 +2108,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
if (!ret)
ret = sdhci_msm_set_vdd_io_vol(msm_host,
VDD_IO_LOW, 0);
if (!ret)
ret = sdhci_msm_set_pincfg(msm_host, false);
if (ret)
irq_ack |= CORE_PWRCTL_BUS_FAIL;
else
@ -3427,7 +3466,7 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
}
static const struct dev_pm_ops sdhci_msm_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
sdhci_msm_runtime_resume,