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msm: kgsl: Fix GPU UBWC setting for DDR 5

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It needs to be 16 instead of 15.

Change-Id: I14e56bfd0b86aa6f3e38af2fc4fa7c1c30adac2e
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt 2020-03-10 17:23:10 -06:00
commit 5b4355dbc4
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/msm/adreno-gpulist.h
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@ -1516,7 +1516,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
.veto_fal10 = true,
.protected_regs = a620_protected_regs,
.disable_tseskip = true,
.highest_bank_bit = 15,
.highest_bank_bit = 16,
.pdc_in_aop = true,
};