clk: qcom: clk-cpu-sdxlemur: Don't limit the max register

The lucid_5lpe PLL has multiple registers past 0x3C, including the
ALPHA_VAL and SSC registers. Since we currently set max_register to
0x3C, this causes read failures on ALPHA_VAL in in
alpha_pll_lucid_recalc_rate(). This function ignores the regmap_read()
return codes, which results in the frac variable being uninitialized.

The CPU PLL doesn't currently use fractional operation, so it should
always be zero in HW. But the uninitialized frac variable causes random,
small increases to the calculated frequency.

Specifying max_register is optional, so just remove it and allow the
full range we define in devicetree.

Change-Id: I3549c249f2dfbad5c056de584864b0e1a3eeb912
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>

drivers/clk/qcom/clk-cpu-sdxlemur.c

@@ -361,7 +361,6 @@ static struct regmap_config cpu_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
-	.max_register	= 0x3C,
 	.fast_io	= true,
 };