mmi_pl_chg: clear pmic limit after remove pd power

the pmic current would be limit when 45w pd charger connect,
and must clear the pmic limit setting after PD power removed.

Change-Id: I814e2825ca29c0975542bda0dcc72f6571ea437a
Signed-off-by: xuwt2 <xuwt2@lenovo.com>
Reviewed-on: https://gerrit.mot.com/1439744
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Jianqi Yang <yangj@motorola.com>
Submit-Approved: Jira Key
Reviewed-on: https://gerrit.mot.com/1893582
Reviewed-by: Wei Xu <xuwei9@lenovo.com>
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
This commit is contained in:
xuwt2 2019-10-21 18:44:03 +08:00 • committed by Wei Xu
commit 5fba839bb3
2 changed files with 4 additions and 0 deletions

View file

@ -941,6 +941,7 @@ static void cancel_sm(struct mmi_charger_manager *chip)
{
cancel_delayed_work_sync(&chip->mmi_chrg_sm_work);
flush_delayed_work(&chip->mmi_chrg_sm_work);
mmi_chrg_policy_clear(chip);
chip->sm_work_running = false;
mmi_chrg_dbg(chip, PR_INTERRUPT,
"cancel sync and flush mmi chrg sm work\n");

View file

@ -293,9 +293,12 @@ static void chrg_policy_error_recovery(struct mmi_charger_manager *chip,
#define PD_CONT_PWR_CNT 5
void mmi_chrg_policy_clear(struct mmi_charger_manager *chip) {
struct mmi_cp_policy_dev *chrg_list = &g_chrg_list;
chrg_dev_init(chip, &g_chrg_list);
clear_chrg_dev_error_cnt(chip, &g_chrg_list);;
clear_chg_manager(chip);
mmi_set_charing_current(chrg_list->chrg_dev[PMIC_SW],
DISABLE_CHRG_LIMIT);
sm_state = PM_STATE_DISCONNECT;
chip->pps_volt_comp = PPS_INIT_VOLT_COMP;
quit_slave_chrg_cnt = 0;