ARM: dts: msm: Correct SVS clock level for IPE0 in Lahaina DT

The SVS clock rate for IPE0 is 450MHz as opposed to 475MHz.
This wrong entry resulted in clock being bumped to NOM instead
of SVS level.

CRs-Fixed: 2745429
Change-Id: I759cff68f3811d9f7c44d2fe99bbc0433895945a
This commit is contained in:
Karthik Anantha Ram 2020-08-03 15:30:12 -07:00
commit 61d0c90232

View file

@ -1808,7 +1808,7 @@
clock-rates =
<0 0 0 300000000 0>,
<0 0 0 475000000 0>,
<0 0 0 450000000 0>,
<0 0 0 525000000 0>,
<0 0 0 700000000 0>,
<0 0 0 700000000 0>;