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ARM: dts: msm: add clk status register for lahaina target

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Add sspp and wb2 clock active status register and
bit offset index for lahaina target. This is required
to check hw blocks' idle vs busy status.

Change-Id: I0834a267e8c4f007a92da0852e33b1e0e02de226
This commit is contained in:
Dhaval Patel 2020-06-17 15:48:15 -07:00 • committed by Gerrit - the friendly Code Review server
commit 658ad44fed
2 changed files with 14 additions and 2 deletions
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12
bindings/sde.txt
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@ -178,10 +178,10 @@ Optional properties:
match the number of offsets defined in
property: qcom,sde-sspp-off
- qcom,sde-sspp-clk-status: Array of offsets describing clk status
offsets for dynamic clock gating. 1st value
offsets for clock active state. 1st value
in the array represents offset of the status
register. 2nd value represents bit offset within
control register. Number of offsets defined should
status register. Number of offsets defined should
match the number of offsets defined in
property: qcom,sde-sspp-off.
- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle
@ -359,6 +359,13 @@ Optional properties:
control register. Number of offsets defined should
match the number of offsets defined in
property: qcom,sde-wb-off
- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status
offsets for clock active state. 1st value
in the array represents offset of the status
register. 2nd value represents bit offset within
status register. Number of offsets defined should
match the number of offsets defined in
property: qcom,sde-wb-off
- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks,
relative to "regdma_phys" defined in reg property.
- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the
@ -724,6 +731,7 @@ Example:
qcom,sde-wb-id = <2>;
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
qcom,sde-wb-clk-status = <0x3bc 20>;
qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff

4
display/lahaina-sde.dtsi
View file

@ -79,6 +79,7 @@
qcom,sde-wb-xin-id = <6>;
qcom,sde-wb-id = <2>;
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
qcom,sde-wb-clk-status = <0x3bc 20>;
qcom,sde-intf-off = <0x35000 0x36000
0x37000 0x38000>;
@ -155,6 +156,9 @@
qcom,sde-sspp-clk-ctrl =
<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
qcom,sde-sspp-clk-status =
<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,
<0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;
qcom,sde-sspp-csc-off = <0x1a00>;
qcom,sde-csc-type = "csc-10bit";
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";