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ARM: dts: msm: Add dmips and dynamic power co-efficient for Yupik

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Add capacity-dmips-mhz and dynamic power coefficient for Yupik, these
are used by Energy aware scheduler for taskplacement decisions.

Change-Id: I922e56d3df8f9c1cfb40ab8cfd77366375875006
This commit is contained in:
Lingutla Chandrasekhar 2020-11-05 16:08:32 +05:30
commit 66008f5ae6
1 changed files with 16 additions and 0 deletions
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16
qcom/yupik.dtsi
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@ -63,6 +63,8 @@
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@ -82,6 +84,8 @@
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@ -96,6 +100,8 @@
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@ -110,6 +116,8 @@
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
@ -124,6 +132,8 @@
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
@ -138,6 +148,8 @@
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
@ -152,6 +164,8 @@
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@ -166,6 +180,8 @@
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1985>;
dynamic-power-coefficient = <552>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";