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Merge "ARM: dts: msm: Add bindings for PCIe end point driver"
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63
bindings/msm_mhi_dev.txt
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63
bindings/msm_mhi_dev.txt
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MSM MHI DEV
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MSM MHI DEV enables communication with the host over a PCIe link using the
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Modem Host Interface protocol. The driver interfaces with the IPA for
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enabling the HW acceleration channel path and provides interface for
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software channels to communicate between Host and device.
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Required properties:
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- compatible: should be "qcom,msm-mhi-dev" for MHI device driver.
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- reg: MHI MMIO physical register space.
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- reg-names: resource names used for the MHI MMIO physical address region,
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IPA uC command and event ring doorbell mail box address.
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Should be "mhi_mmio_base" for MHI MMIO physical address,
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"ipa_uc_mbox_crdb" for IPA uC Command Ring doorbell,
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"ipa_uc_mbox_erdb" for IPA uC Event Ring doorbell passed to
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the IPA driver.
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- qcom,mhi-ifc-id: ID of HW interface via which MHI on device side
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communicates with host side.
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- qcom,mhi-ep-msi: End point MSI number.
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- qcom,mhi-version: MHI specification version supported by the device.
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Optional property:
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- qcom,use-ipa-software-channel: If property is present use IPA hardware
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accelerated path for MHI software channel data transfers
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between host and device.
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- qcom,mhi-config-iatu: If property is present map the control and data region
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between host and device using iatu.
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- qcom,mhi-interrupt: If property is present register for mhi interrupt.
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- qcom,mhi-local-pa-base: The physical base address on the device used by the
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MHI device driver to map the control and data region with the
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MHI driver on the host. This property is required if iatu
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property qcom,mhi-config-iatu is present.
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- qcom,enable-m2: If property is present M2 autonomous is enabled.
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MSM MHI DEV NET
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MSM MHI DEV enables communication with the host over a PCIe link using the
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Network Interface.
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Required properties:
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- compatible: should be "qcom,msm-mhi-dev-net" for MHI net device driver.
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Optional property:
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- qcom,mhi-ethernet-interface;: If property is present use ethernet packet
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parsing support.
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Example:
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mhi: qcom,msm-mhi-dev {
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compatible = "qcom,msm-mhi-dev";
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reg = <0xfc527000 0x1000>,
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<0xfd4fa000 0x1>,
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<0xfd4fa080 0x1>;
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reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb",
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"ipa_uc_mbox_erdb";
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qcom,mhi-ifc-id = <0x030017cb>;
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qcom,mhi-ep-msi = <1>;
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qcom,mhi-version = <0x1000000>;
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};
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qcom,mhi_net_dev {
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compatible = "qcom,msm-mhi-dev-net";
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qcom,mhi-ethernet-interface;
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};
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153
bindings/pci/msm_ep_pcie.txt
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153
bindings/pci/msm_ep_pcie.txt
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MSM PCI express endpoint
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Required properties:
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- compatible: should be "qcom,pcie-ep".
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- reg: should contain PCIe register maps.
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- reg-names: indicates various resources passed to driver by name.
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Should be "msi", "dm_core", "elbi", "parf", "phy", "mmio",
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"tcsr_pcie_perst_en".
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These correspond to different modules within the PCIe domain.
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- #address-cells: Should provide a value of 0.
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- interrupt-parent: Should be the PCIe device node itself here.
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- interrupts: Should be in the format <0 1 2> and it is an index to the
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interrupt-map that contains PCIe related interrupts.
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- #interrupt-cells: Should provide a value of 1.
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- #interrupt-map-mask: should provide a value of 0xffffffff.
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- interrupt-map: Must create mapping for the number of interrupts
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that are defined in above interrupts property.
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For PCIe device node, it should define 6 mappings for
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the corresponding PCIe interrupts supporting the
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specification.
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- interrupt-names: indicates interrupts passed to driver by name.
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Should be "int_pm_turnoff", "int_dstate_change",
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"int_l1sub_timeout", "int_link_up",
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"int_link_down", "int_bridge_flush_n".
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- perst-gpio: PERST GPIO specified by PCIe spec.
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- wake-gpio: WAKE GPIO specified by PCIe spec.
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- clkreq-gpio: CLKREQ GPIO specified by PCIe spec.
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- <supply-name>-supply: phandle to the regulator device tree node.
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Refer to the schematics for the corresponding voltage regulators.
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vreg-1.8-supply: phandle to the analog supply for the PCIe controller.
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vreg-0.9-supply: phandle to the analog supply for the PCIe controller.
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Optional Properties:
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- qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
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Should be specified in pairs (max, min, optimal), units uV.
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- clock-names: list of names of clock inputs.
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Should be "pcie_pipe_clk",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_ldo";
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- max-clock-frequency-hz: list of the maximum operating frequencies stored
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in the same order of clock names;
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- resets: reset specifier pair consists of phandle for the reset controller
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and reset lines used by this controller.
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- reset-names: reset signal names sorted in the same order as the property
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of resets.
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- qcom,pcie-phy-ver: version of PCIe PHY.
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- qcom,phy-init: The initialization sequence to bring up the PCIe PHY.
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Should be specified in groups (offset, value, delay, direction).
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- qcom,phy-status-reg: Register offset for PHY status.
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- qcom,phy-status-reg2: For sdxprairie and above use only
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qcom,phy-status-reg2 as register offset for PHY status.
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- qcom,dbi-base-reg: Register offset for DBI base address.
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- qcom,slv-space-reg: Register offset for slave address space size.
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- qcom,pcie-vendor-id: Vendor id to be written to the Vendor ID register.
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- qcom,pcie-device-id: Device id to be written to the Device ID register.
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- qcom,pcie-link-speed: generation of PCIe link speed. The value could be
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1, 2 or 3.
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- qcom,pcie-active-config: boolean type; active configuration of PCIe
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addressing.
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- qcom,pcie-edma: boolean type; edma usage for PCIe.
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- qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated.
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- qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq.
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- qcom,pcie-perst-enum: Link enumeration will be triggered by PERST
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deassertion.
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- qcom,tcsr-not-supported: TCSR pcie perst is not supported.
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- mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side.
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- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
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below optional properties:
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- qcom,msm-bus,name
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- qcom,msm-bus,num-cases
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- qcom,msm-bus,num-paths
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- qcom,msm-bus,vectors-KBps
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- qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode.
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- qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset.
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Example:
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pcie_ep: qcom,pcie@bfffd000 {
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compatible = "qcom,pcie-ep";
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reg = <0xbfffd000 0x1000>,
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<0xbfffe000 0x1000>,
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<0xbffff000 0x1000>,
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<0xfc520000 0x2000>,
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<0xfc526000 0x1000>,
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<0xfc527000 0x1000>,
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<0x01fcb000 0x1000>;
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reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio",
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"tcsr_pcie_perst";
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#address-cells = <0>;
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interrupt-parent = <&pcie_ep>;
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interrupts = <0 1 2 3 4 5>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 44 0
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1 &intc 0 46 0
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2 &intc 0 47 0
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3 &intc 0 50 0
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4 &intc 0 51 0
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5 &intc 0 52 0>;
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interrupt-names = "int_pm_turnoff", "int_dstate_change",
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"int_l1sub_timeout", "int_link_up",
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"int_link_down", "int_bridge_flush_n";
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perst-gpio = <&msmgpio 65 0>;
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wake-gpio = <&msmgpio 61 0>;
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clkreq-gpio = <&msmgpio 64 0>;
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mdm2apstatus-gpio = <&tlmm_pinmux 16 0>;
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gdsc-vdd-supply = <&gdsc_pcie_0>;
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vreg-1.8-supply = <&pmd9635_l8>;
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vreg-0.9-supply = <&pmd9635_l4>;
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qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
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qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
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clock-names = "pcie_pipe_clk",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_ldo";
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max-clock-frequency-hz = <62500000>, <1000000>,
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<0>, <0>, <0>, <0>;
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resets = <&clock_gcc GCC_PCIE_BCR>,
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<&clock_gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_core_reset", "pcie_phy_reset";
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qcom,msm-bus,name = "pcie-ep";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>,
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<45 512 500 800>;
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qcom,pcie-link-speed = <1>;
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qcom,pcie-active-config;
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qcom,pcie-aggregated-irq;
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qcom,pcie-mhi-a7-irq;
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qcom,pcie-perst-enum;
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qcom,phy-status-reg = <0x728>;
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qcom,dbi-base-reg = <0x168>;
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qcom,slv-space-reg = <0x16c>;
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qcom,phy-init = <0x604 0x03 0x0 0x1
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0x048 0x08 0x0 0x1
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0x64c 0x4d 0x0 0x1
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0x600 0x00 0x0 0x1
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0x608 0x03 0x0 0x1>;
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};
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