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ARM: dts: msm: Add support for SCM PAS
The PIL drivers need to vote for bandwidth across DDR and crypto subsytem, such that the secure world can perform initialization and authorization of the firmware blobs. Hence add a device-tree node indicating the corresponding interconnect. Change-Id: If5626ad20638434e39a7d4aa0f02149a72bdaf12
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@ -556,6 +556,11 @@
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#interconnect-cells = <1>;
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};
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pil_scm_pas {
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compatible = "qcom,pil-tz-scm-pas";
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interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
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};
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ufsphy_mem: ufsphy_mem@1d87000 {
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reg = <0x1d8700 0xe10>;
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reg-names = "phy_mem";
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