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clk: qcom: Update parent map to use parent_map struct

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Add support to use parent_map structure for mux clk parent.

Change-Id: I3f3655387bd8a7a3046a801ece921576d4e69e4b
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
This commit is contained in:
Naveen Yadav 2020-09-18 20:09:58 +05:30
commit 68840cf253
2 changed files with 7 additions and 7 deletions
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10
drivers/clk/qcom/clk-regmap-mux-div.c
View file

@ -150,7 +150,7 @@ static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
if (is_better_rate(rate, best_rate, actual_rate)) {
best_rate = actual_rate;
best_src = md->parent_map[i];
best_src = md->parent_map[i].cfg;
best_div = div - 1;
}
@ -177,7 +177,7 @@ static u8 mux_div_get_parent(struct clk_hw *hw)
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (src == md->parent_map[i])
if (src == md->parent_map[i].cfg)
return i;
pr_err("%s: Can't find parent with src %d\n", name, src);
@ -188,7 +188,7 @@ static int mux_div_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return mux_div_set_src_div(md, md->parent_map[index], md->div);
return mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
}
static int mux_div_set_rate(struct clk_hw *hw,
@ -205,7 +205,7 @@ static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return __mux_div_set_rate_and_parent(hw, rate, prate,
md->parent_map[index]);
md->parent_map[index].cfg);
}
static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
@ -217,7 +217,7 @@ static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < num_parents; i++)
if (src == md->parent_map[i]) {
if (src == md->parent_map[i].cfg) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
unsigned long parent_rate = clk_hw_get_rate(p);

4
drivers/clk/qcom/clk-regmap-mux-div.h
View file

@ -19,7 +19,7 @@
* @src_shift: lowest bit of source select field
* @div: the divider raw configuration value
* @src: the mux index which will be used if the clock is enabled
* @parent_map: map from parent_names index to src_sel field
* @parent_map: pointer to parent_map struct
* @clkr: handle between common and hardware-specific interfaces
* @pclk: the input PLL clock
* @clk_nb: clock notifier for rate changes of the input PLL
@ -32,7 +32,7 @@ struct clk_regmap_mux_div {
u32 src_shift;
u32 div;
u32 src;
const u32 *parent_map;
const struct parent_map *parent_map;
struct clk_regmap clkr;
struct clk *pclk;
struct notifier_block clk_nb;