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Merge 78f83a4079 on remote branch

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Change-Id: Ic9d9d9d452dec3f4e10cb6c0e099d561fb869514
This commit is contained in:
Linux Build Service Account 2021-08-13 00:44:50 -07:00
commit 723b1eff44
8 changed files with 273 additions and 4 deletions
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7
drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
View file

@ -27,6 +27,7 @@
#include "cpastop_v580_custom.h"
#include "cpastop_v540_100.h"
#include "cpastop_v520_100.h"
#include "cpastop_v520_110.h"
#include "cpastop_v545_100.h"
#include "cpastop_v545_110.h"
#include "cpastop_v570_200.h"
@ -102,7 +103,7 @@ static const uint32_t cam_cpas_hw_version_map
{
CAM_CPAS_TITAN_520_V100,
0,
0,
CAM_CPAS_TITAN_520_V110,
0,
0,
0,
@ -934,6 +935,10 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
camnoc_info = &cam520_cpas100_camnoc_info;
qchannel_info = &cam520_cpas100_qchannel_info;
break;
case CAM_CPAS_TITAN_520_V110:
camnoc_info = &cam520_cpas110_camnoc_info;
qchannel_info = &cam520_cpas110_qchannel_info;
break;
case CAM_CPAS_TITAN_545_V100:
camnoc_info = &cam545_cpas100_camnoc_info;
qchannel_info = &cam545_cpas100_qchannel_info;

244
drivers/cam_cpas/cpas_top/cpastop_v520_110.h Normal file
View file

@ -0,0 +1,244 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CPASTOP_V520_110_H_
#define _CPASTOP_V520_110_H_
#define TEST_IRQ_ENABLE 0
static struct cam_camnoc_irq_sbm cam_cpas_v520_110_irq_sbm = {
.sbm_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
(TEST_IRQ_ENABLE ?
0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */,
},
.sbm_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */
},
.sbm_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
.value = TEST_IRQ_ENABLE ? 0x3 : 0x1,
}
};
static struct cam_camnoc_irq_err
cam_cpas_v520_110_irq_err[] = {
{
.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
.enable = true,
.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */
.value = 1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */
},
.err_clear = {
.access_type = CAM_REG_TYPE_WRITE,
.enable = true,
.offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */
.value = 1,
},
},
{
.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
.enable = TEST_IRQ_ENABLE ? true : false,
.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
.err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true,
.offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */
.value = 0x1,
},
.err_status = {
.access_type = CAM_REG_TYPE_READ,
.enable = true,
.offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */
},
.err_clear = {
.enable = false,
},
},
};
static struct cam_camnoc_specific
cam_cpas_v520_110_camnoc_specific[] = {
{
.port_type = CAM_CAMNOC_CDM,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE30, /* CDM_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE38, /* CDM_URGENCY_LOW */
.value = 0x00000003,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE40, /* CDM_DANGERLUT_LOW */
.value = 0x0,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE48, /* CDM_SAFELUT_LOW */
.value = 0x0,
},
.ubwc_ctl = {
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_TFE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_LOW */
.offset = 0x30,
.value = 0x44443333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
/* TFE_PRIORITYLUT_HIGH */
.offset = 0x34,
.value = 0x66665555,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x38, /* TFE_URGENCY_LOW */
.value = 0x00001030,
},
.danger_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x40, /* TFE_DANGERLUT_LOW */
.value = 0xffff0000,
},
.safe_lut = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x48, /* TFE_SAFELUT_LOW */
.value = 0x00000003,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
{
.port_type = CAM_CAMNOC_OPE,
.enable = true,
.priority_lut_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* OPE_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */
.value = 0x33333333,
},
.urgency = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x438, /* OPE_URGENCY_LOW */
.value = 0x00000033,
},
.danger_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x440, /* OPE_DANGERLUT_LOW */
.value = 0xFFFFFF00,
},
.safe_lut = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x448, /* OPE_SAFELUT_LOW */
.value = 0xF,
},
.ubwc_ctl = {
/*
* Do not explicitly set ubwc config register.
* Power on default values are taking care of required
* register settings.
*/
.enable = false,
},
},
};
static struct cam_camnoc_err_logger_info cam520_cpas110_err_logger_offsets = {
.mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */
.errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */
.errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */
.errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */
.errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */
.errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */
.errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */
.errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */
.errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */
.errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */
};
static struct cam_camnoc_info cam520_cpas110_camnoc_info = {
.specific = &cam_cpas_v520_110_camnoc_specific[0],
.specific_size = ARRAY_SIZE(cam_cpas_v520_110_camnoc_specific),
.irq_sbm = &cam_cpas_v520_110_irq_sbm,
.irq_err = &cam_cpas_v520_110_irq_err[0],
.irq_err_size = ARRAY_SIZE(cam_cpas_v520_110_irq_err),
.err_logger = &cam520_cpas110_err_logger_offsets,
.errata_wa_list = NULL,
};
static struct cam_cpas_camnoc_qchannel cam520_cpas110_qchannel_info = {
.qchannel_ctrl = 0x14,
.qchannel_status = 0x18,
};
#endif /* _CPASTOP_V520_110_H_ */

4
drivers/cam_cpas/cpas_top/cpastop_v545_110.h
View file

@ -250,14 +250,14 @@ static struct cam_camnoc_specific
.port_type = CAM_CAMNOC_OPE,
.enable = true,
.priority_lut_low = {
.enable = false,
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x430, /* OPE_PRIORITYLUT_LOW */
.value = 0x33333333,
},
.priority_lut_high = {
.enable = false,
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */

1
drivers/cam_cpas/include/cam_cpas_api.h
View file

@ -138,6 +138,7 @@ enum cam_cpas_hw_version {
CAM_CPAS_TITAN_580_V100 = 0x580100,
CAM_CPAS_TITAN_540_V100 = 0x540100,
CAM_CPAS_TITAN_520_V100 = 0x520100,
CAM_CPAS_TITAN_520_V110 = 0x520110,
CAM_CPAS_TITAN_545_V100 = 0x545100,
CAM_CPAS_TITAN_545_V110 = 0x545110,
CAM_CPAS_TITAN_570_V200 = 0x570200,

6
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
View file

@ -405,6 +405,12 @@ static int cam_vfe_hw_dump(
return -ENOSPC;
}
dump_data = top_priv->common_data.dump_data;
if (!dump_data) {
CAM_ERR(CAM_ISP, "Dump data not available");
return -EINVAL;
}
soc_info = top_priv->common_data.soc_info;
/*Dump registers */

7
drivers/cam_req_mgr/cam_req_mgr_core.c
View file

@ -2913,6 +2913,13 @@ int cam_req_mgr_process_error(void *priv, void *data)
in_q->rd_idx = idx;
in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED;
if (link->sync_link[0]) {
in_q->slot[idx].sync_mode = 0;
__cam_req_mgr_inc_idx(&idx, 1,
link->req.l_tbl->num_slots);
in_q->slot[idx].sync_mode = 0;
}
/* The next req may also be applied */
idx = in_q->rd_idx;
__cam_req_mgr_inc_idx(&idx, 1,

6
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
View file

@ -153,6 +153,12 @@ static void cam_csiphy_prgm_cmn_data(
csiphybase = g_phy_data[csiphy_idx].base_address;
is_3phase = g_phy_data[csiphy_idx].is_3phase;
if (!csiphybase) {
CAM_DBG(CAM_CSIPHY, "CSIPHY: %d is not available in platform",
csiphy_idx);
continue;
}
for (i = 0; i < size; i++) {
csiphy_common_reg =
&csiphy_dev->ctrl_reg->csiphy_common_reg[i];

2
drivers/cam_utils/cam_soc_icc.c
View file

@ -103,7 +103,7 @@ int cam_soc_bus_client_register(struct platform_device *pdev,
bus_client_data->icc_data = icc_get(&pdev->dev,
bus_client->common_data->src_id,
bus_client->common_data->dst_id);
if (!bus_client_data->icc_data) {
if (IS_ERR_OR_NULL(bus_client_data->icc_data)) {
CAM_ERR(CAM_UTIL, "failed in register bus client");
rc = -EINVAL;
goto error;