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Merge "clk: qcom: gcc-lahaina: Add USB force_mem_core_on clocks"

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This commit is contained in:
qctecmdr 2020-06-05 00:39:02 -07:00 • committed by Gerrit - the friendly Code Review server
commit 732adf0e7c
2 changed files with 58 additions and 26 deletions
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30
drivers/clk/qcom/gcc-lahaina.c
View file

@ -3795,6 +3795,19 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
},
};
static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
@ -3845,6 +3858,19 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
},
};
static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
@ -4244,6 +4270,8 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
@ -4252,6 +4280,8 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =

54
include/dt-bindings/clock/qcom,gcc-lahaina.h
View file

@ -188,32 +188,34 @@
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 176
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 177
#define GCC_USB30_PRIM_MASTER_CLK 178
#define GCC_USB30_PRIM_MASTER_CLK_SRC 179
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 180
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 181
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 182
#define GCC_USB30_PRIM_SLEEP_CLK 183
#define GCC_USB30_SEC_MASTER_CLK 184
#define GCC_USB30_SEC_MASTER_CLK_SRC 185
#define GCC_USB30_SEC_MOCK_UTMI_CLK 186
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 187
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 188
#define GCC_USB30_SEC_SLEEP_CLK 189
#define GCC_USB3_PRIM_PHY_AUX_CLK 190
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 191
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 192
#define GCC_USB3_PRIM_PHY_PIPE_CLK 193
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 194
#define GCC_USB3_SEC_CLKREF_EN 195
#define GCC_USB3_SEC_PHY_AUX_CLK 196
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 197
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 198
#define GCC_USB3_SEC_PHY_PIPE_CLK 199
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 200
#define GCC_VIDEO_AHB_CLK 201
#define GCC_VIDEO_AXI0_CLK 202
#define GCC_VIDEO_AXI1_CLK 203
#define GCC_VIDEO_XO_CLK 204
#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 179
#define GCC_USB30_PRIM_MASTER_CLK_SRC 180
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 181
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 182
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 183
#define GCC_USB30_PRIM_SLEEP_CLK 184
#define GCC_USB30_SEC_MASTER_CLK 185
#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 186
#define GCC_USB30_SEC_MASTER_CLK_SRC 187
#define GCC_USB30_SEC_MOCK_UTMI_CLK 188
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 189
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 190
#define GCC_USB30_SEC_SLEEP_CLK 191
#define GCC_USB3_PRIM_PHY_AUX_CLK 192
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 193
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 194
#define GCC_USB3_PRIM_PHY_PIPE_CLK 195
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 196
#define GCC_USB3_SEC_CLKREF_EN 197
#define GCC_USB3_SEC_PHY_AUX_CLK 198
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 199
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 200
#define GCC_USB3_SEC_PHY_PIPE_CLK 201
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 202
#define GCC_VIDEO_AHB_CLK 203
#define GCC_VIDEO_AXI0_CLK 204
#define GCC_VIDEO_AXI1_CLK 205
#define GCC_VIDEO_XO_CLK 206
/* GCC resets */
#define GCC_CAMERA_BCR 0